wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * cpu.c |
| 26 | * |
| 27 | * CPU specific code |
| 28 | * |
| 29 | * written or collected and sometimes rewritten by |
| 30 | * Magnus Damm <damm@bitsmart.com> |
| 31 | * |
| 32 | * minor modifications by |
| 33 | * Wolfgang Denk <wd@denx.de> |
| 34 | * |
| 35 | * more modifications by |
| 36 | * Josh Huber <huber@mclx.com> |
| 37 | * added support for the 74xx series of cpus |
| 38 | * added support for the 7xx series of cpus |
| 39 | * made the code a little less hard-coded, and more auto-detectish |
| 40 | */ |
| 41 | |
| 42 | #include <common.h> |
| 43 | #include <command.h> |
| 44 | #include <74xx_7xx.h> |
| 45 | #include <asm/cache.h> |
| 46 | |
Gerald Van Baren | 589c042 | 2008-06-03 20:24:58 -0400 | [diff] [blame] | 47 | #if defined(CONFIG_OF_LIBFDT) |
| 48 | #include <libfdt.h> |
| 49 | #include <fdt_support.h> |
| 50 | #endif |
| 51 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 52 | DECLARE_GLOBAL_DATA_PTR; |
| 53 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 54 | cpu_t |
| 55 | get_cpu_type(void) |
| 56 | { |
| 57 | uint pvr = get_pvr(); |
| 58 | cpu_t type; |
| 59 | |
| 60 | type = CPU_UNKNOWN; |
| 61 | |
| 62 | switch (PVR_VER(pvr)) { |
| 63 | case 0x000c: |
| 64 | type = CPU_7400; |
| 65 | break; |
| 66 | case 0x0008: |
| 67 | type = CPU_750; |
| 68 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 69 | if (((pvr >> 8) & 0xff) == 0x01) { |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 70 | type = CPU_750CX; /* old CX (80100 and 8010x?)*/ |
| 71 | } else if (((pvr >> 8) & 0xff) == 0x22) { |
| 72 | type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */ |
| 73 | } else if (((pvr >> 8) & 0xff) == 0x33) { |
| 74 | type = CPU_750CX; /* CXe (83311) */ |
| 75 | } else if (((pvr >> 12) & 0xF) == 0x3) { |
| 76 | type = CPU_755; |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 77 | } |
| 78 | break; |
| 79 | |
| 80 | case 0x7000: |
| 81 | type = CPU_750FX; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 82 | break; |
| 83 | |
wdenk | 3a473b2 | 2004-01-03 00:43:19 +0000 | [diff] [blame] | 84 | case 0x7002: |
| 85 | type = CPU_750GX; |
| 86 | break; |
| 87 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 88 | case 0x800C: |
| 89 | type = CPU_7410; |
| 90 | break; |
| 91 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 92 | case 0x8000: |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 93 | type = CPU_7450; |
| 94 | break; |
| 95 | |
wdenk | 3a473b2 | 2004-01-03 00:43:19 +0000 | [diff] [blame] | 96 | case 0x8001: |
| 97 | type = CPU_7455; |
| 98 | break; |
| 99 | |
| 100 | case 0x8002: |
| 101 | type = CPU_7457; |
| 102 | break; |
| 103 | |
roy zang | 4c52783 | 2006-11-02 18:49:51 +0800 | [diff] [blame] | 104 | case 0x8003: |
| 105 | type = CPU_7447A; |
| 106 | break; |
roy zang | c9c1eee | 2006-12-01 19:01:25 +0800 | [diff] [blame] | 107 | |
roy zang | 4c52783 | 2006-11-02 18:49:51 +0800 | [diff] [blame] | 108 | case 0x8004: |
| 109 | type = CPU_7448; |
| 110 | break; |
roy zang | c9c1eee | 2006-12-01 19:01:25 +0800 | [diff] [blame] | 111 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 112 | default: |
| 113 | break; |
| 114 | } |
| 115 | |
| 116 | return type; |
| 117 | } |
| 118 | |
| 119 | /* ------------------------------------------------------------------------- */ |
| 120 | |
| 121 | #if !defined(CONFIG_BAB7xx) |
| 122 | int checkcpu (void) |
| 123 | { |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 124 | uint type = get_cpu_type(); |
| 125 | uint pvr = get_pvr(); |
| 126 | ulong clock = gd->cpu_clk; |
| 127 | char buf[32]; |
| 128 | char *str; |
| 129 | |
| 130 | puts ("CPU: "); |
| 131 | |
| 132 | switch (type) { |
| 133 | case CPU_750CX: |
| 134 | printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"", |
| 135 | (pvr>>8) & 0xf, |
| 136 | pvr & 0xf); |
| 137 | goto PR_CLK; |
| 138 | |
| 139 | case CPU_750: |
| 140 | str = "750"; |
| 141 | break; |
| 142 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 143 | case CPU_750FX: |
| 144 | str = "750FX"; |
| 145 | break; |
| 146 | |
wdenk | 3a473b2 | 2004-01-03 00:43:19 +0000 | [diff] [blame] | 147 | case CPU_750GX: |
| 148 | str = "750GX"; |
| 149 | break; |
| 150 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 151 | case CPU_755: |
| 152 | str = "755"; |
| 153 | break; |
| 154 | |
| 155 | case CPU_7400: |
| 156 | str = "MPC7400"; |
| 157 | break; |
| 158 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 159 | case CPU_7410: |
| 160 | str = "MPC7410"; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 161 | break; |
| 162 | |
roy zang | c9c1eee | 2006-12-01 19:01:25 +0800 | [diff] [blame] | 163 | case CPU_7447A: |
| 164 | str = "MPC7447A"; |
| 165 | break; |
| 166 | |
Stefan Roese | 1eac2a7 | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 167 | case CPU_7448: |
| 168 | str = "MPC7448"; |
| 169 | break; |
| 170 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 171 | case CPU_7450: |
| 172 | str = "MPC7450"; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 173 | break; |
| 174 | |
wdenk | 3a473b2 | 2004-01-03 00:43:19 +0000 | [diff] [blame] | 175 | case CPU_7455: |
| 176 | str = "MPC7455"; |
| 177 | break; |
| 178 | |
| 179 | case CPU_7457: |
| 180 | str = "MPC7457"; |
| 181 | break; |
| 182 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 183 | default: |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 184 | printf("Unknown CPU -- PVR: 0x%08x\n", pvr); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 185 | return -1; |
| 186 | } |
| 187 | |
| 188 | printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF); |
| 189 | PR_CLK: |
| 190 | printf (" @ %s MHz\n", strmhz(buf, clock)); |
| 191 | |
| 192 | return (0); |
| 193 | } |
| 194 | #endif |
| 195 | /* these two functions are unimplemented currently [josh] */ |
| 196 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 197 | /* -------------------------------------------------------------------- */ |
| 198 | /* L1 i-cache */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 199 | |
| 200 | int |
| 201 | checkicache(void) |
| 202 | { |
| 203 | return 0; /* XXX */ |
| 204 | } |
| 205 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 206 | /* -------------------------------------------------------------------- */ |
| 207 | /* L1 d-cache */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 208 | |
| 209 | int |
| 210 | checkdcache(void) |
| 211 | { |
| 212 | return 0; /* XXX */ |
| 213 | } |
| 214 | |
wdenk | 72755c7 | 2003-06-20 23:10:58 +0000 | [diff] [blame] | 215 | /* -------------------------------------------------------------------- */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 216 | |
| 217 | static inline void |
| 218 | soft_restart(unsigned long addr) |
| 219 | { |
| 220 | /* SRR0 has system reset vector, SRR1 has default MSR value */ |
| 221 | /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ |
| 222 | |
| 223 | __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); |
| 224 | __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); |
| 225 | __asm__ __volatile__ ("mtspr 27, 4"); |
| 226 | __asm__ __volatile__ ("rfi"); |
| 227 | |
| 228 | while(1); /* not reached */ |
| 229 | } |
| 230 | |
| 231 | |
Stefan Roese | 7c9e89b | 2013-02-07 01:48:30 +0000 | [diff] [blame] | 232 | #if !defined(CONFIG_BAB7xx) && \ |
Heiko Schocher | f5e0d03 | 2006-06-19 11:02:41 +0200 | [diff] [blame] | 233 | !defined(CONFIG_ELPPC) && \ |
| 234 | !defined(CONFIG_PPMC7XX) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 235 | /* no generic way to do board reset. simply call soft_reset. */ |
Peter Tyser | c22a711 | 2010-12-03 10:28:47 -0600 | [diff] [blame] | 236 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 237 | { |
Wolfgang Denk | dd520bf | 2006-11-30 18:02:20 +0100 | [diff] [blame] | 238 | ulong addr; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 239 | /* flush and disable I/D cache */ |
| 240 | __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); |
| 241 | __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); |
| 242 | __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); |
| 243 | __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); |
| 244 | __asm__ __volatile__ ("sync"); |
| 245 | __asm__ __volatile__ ("mtspr 1008, 4"); |
| 246 | __asm__ __volatile__ ("isync"); |
| 247 | __asm__ __volatile__ ("sync"); |
| 248 | __asm__ __volatile__ ("mtspr 1008, 5"); |
| 249 | __asm__ __volatile__ ("isync"); |
| 250 | __asm__ __volatile__ ("sync"); |
| 251 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 252 | #ifdef CONFIG_SYS_RESET_ADDRESS |
| 253 | addr = CONFIG_SYS_RESET_ADDRESS; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 254 | #else |
| 255 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, |
| 257 | * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 258 | * address. Better pick an address known to be invalid on your |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | * system and assign it to CONFIG_SYS_RESET_ADDRESS. |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 260 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 262 | #endif |
| 263 | soft_restart(addr); |
Peter Tyser | c22a711 | 2010-12-03 10:28:47 -0600 | [diff] [blame] | 264 | |
| 265 | /* not reached */ |
| 266 | while(1) |
| 267 | ; |
| 268 | |
| 269 | return 1; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 270 | } |
| 271 | #endif |
| 272 | |
| 273 | /* ------------------------------------------------------------------------- */ |
| 274 | |
| 275 | /* |
| 276 | * For the 7400 the TB clock runs at 1/4 the cpu bus speed. |
| 277 | */ |
Wolfgang Denk | 953b7e6 | 2010-06-13 18:28:54 +0200 | [diff] [blame] | 278 | #ifndef CONFIG_SYS_BUS_CLK |
Wolfgang Denk | ee80fa7 | 2010-06-13 18:38:23 +0200 | [diff] [blame] | 279 | #define CONFIG_SYS_BUS_CLK gd->bus_clk |
| 280 | #endif |
| 281 | |
wdenk | c7de829 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 282 | unsigned long get_tbclk(void) |
| 283 | { |
Wolfgang Denk | ee80fa7 | 2010-06-13 18:38:23 +0200 | [diff] [blame] | 284 | return CONFIG_SYS_BUS_CLK / 4; |
wdenk | c7de829 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 285 | } |
wdenk | c7de829 | 2002-11-19 11:04:11 +0000 | [diff] [blame] | 286 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 287 | /* ------------------------------------------------------------------------- */ |
Wolfgang Denk | ee80fa7 | 2010-06-13 18:38:23 +0200 | [diff] [blame] | 288 | |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 289 | #if defined(CONFIG_WATCHDOG) |
Stefan Roese | 7c9e89b | 2013-02-07 01:48:30 +0000 | [diff] [blame] | 290 | #if !defined(CONFIG_BAB7xx) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 291 | void |
| 292 | watchdog_reset(void) |
| 293 | { |
| 294 | |
| 295 | } |
Stefan Roese | 7c9e89b | 2013-02-07 01:48:30 +0000 | [diff] [blame] | 296 | #endif /* !CONFIG_BAB7xx */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 297 | #endif /* CONFIG_WATCHDOG */ |
| 298 | |
| 299 | /* ------------------------------------------------------------------------- */ |
roy zang | 4c52783 | 2006-11-02 18:49:51 +0800 | [diff] [blame] | 300 | |
Gerald Van Baren | 589c042 | 2008-06-03 20:24:58 -0400 | [diff] [blame] | 301 | #ifdef CONFIG_OF_LIBFDT |
| 302 | void ft_cpu_setup(void *blob, bd_t *bd) |
roy zang | 4c52783 | 2006-11-02 18:49:51 +0800 | [diff] [blame] | 303 | { |
Gerald Van Baren | 589c042 | 2008-06-03 20:24:58 -0400 | [diff] [blame] | 304 | do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, |
| 305 | "timebase-frequency", bd->bi_busfreq / 4, 1); |
| 306 | do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, |
| 307 | "bus-frequency", bd->bi_busfreq, 1); |
| 308 | do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, |
| 309 | "clock-frequency", bd->bi_intfreq, 1); |
Wolfgang Denk | 647d3c3 | 2007-03-04 01:36:05 +0100 | [diff] [blame] | 310 | |
Gerald Van Baren | 589c042 | 2008-06-03 20:24:58 -0400 | [diff] [blame] | 311 | fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); |
Wolfgang Denk | 647d3c3 | 2007-03-04 01:36:05 +0100 | [diff] [blame] | 312 | |
Kumar Gala | ba37aa0 | 2008-08-19 15:41:18 -0500 | [diff] [blame] | 313 | fdt_fixup_ethernet(blob); |
roy zang | 4c52783 | 2006-11-02 18:49:51 +0800 | [diff] [blame] | 314 | } |
| 315 | #endif |
| 316 | /* ------------------------------------------------------------------------- */ |