blob: 98602f889ec67fdfd1678851b546ebd983f849f9 [file] [log] [blame]
Fabio Estevam7dd65452012-09-24 08:09:33 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Fabio Estevam7dd65452012-09-24 08:09:33 +00007 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
Eric Nelsonb47abc32013-11-13 16:36:19 -070014#include <asm/arch/mx6-pins.h>
Fabio Estevam7dd65452012-09-24 08:09:33 +000015#include <asm/errno.h>
16#include <asm/gpio.h>
17#include <asm/imx-common/iomux-v3.h>
Renato Frias19578162013-05-13 18:01:12 +000018#include <asm/imx-common/mxc_i2c.h>
Otavio Salvador85449db2013-03-16 08:05:07 +000019#include <asm/imx-common/boot_mode.h>
Eric Nelson3acb0112014-09-30 15:40:03 -070020#include <asm/imx-common/spi.h>
Fabio Estevam7dd65452012-09-24 08:09:33 +000021#include <mmc.h>
22#include <fsl_esdhc.h>
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000023#include <miiphy.h>
24#include <netdev.h>
Fabio Estevamdce67bd2012-10-02 11:20:12 +000025#include <asm/arch/sys_proto.h>
Renato Frias19578162013-05-13 18:01:12 +000026#include <i2c.h>
Fabio Estevam510922a2014-09-22 13:55:52 -030027#include <asm/arch/mxc_hdmi.h>
28#include <asm/imx-common/video.h>
29#include <asm/arch/crm_regs.h>
Ye.Li8fe280f2014-10-30 18:53:49 +080030#include <pca953x.h>
Ye.Li593243d2014-11-06 16:29:02 +080031#include <power/pmic.h>
Peng Fan258c98f2015-01-27 10:14:04 +080032#include <power/pfuze100_pmic.h>
Ye.Li593243d2014-11-06 16:29:02 +080033#include "../common/pfuze.h"
Fabio Estevamdce67bd2012-10-02 11:20:12 +000034
Fabio Estevam7dd65452012-09-24 08:09:33 +000035DECLARE_GLOBAL_DATA_PTR;
36
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000037#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevam7dd65452012-09-24 08:09:33 +000040
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000041#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevam7dd65452012-09-24 08:09:33 +000044
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000045#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000047
Renato Frias19578162013-05-13 18:01:12 +000048#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
Ye.Li83bb3212014-11-12 14:02:05 +080052#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
53#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
54 PAD_CTL_SRE_FAST)
55#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
56
Renato Frias19578162013-05-13 18:01:12 +000057#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58
Fabio Estevamcdbdde32014-11-14 11:27:23 -020059#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
Ye.Li593243d2014-11-06 16:29:02 +080063#define I2C_PMIC 1
64
Fabio Estevam7dd65452012-09-24 08:09:33 +000065int dram_init(void)
66{
67 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
68
69 return 0;
70}
71
Fabio Estevam067a6592014-09-13 18:21:36 -030072static iomux_v3_cfg_t const uart4_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -070073 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
Fabio Estevam7dd65452012-09-24 08:09:33 +000075};
76
Fabio Estevam067a6592014-09-13 18:21:36 -030077static iomux_v3_cfg_t const enet_pads[] = {
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000078 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelson10fda482013-11-04 17:00:51 -070080 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000085 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelson10fda482013-11-04 17:00:51 -070087 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000092 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000093};
94
Renato Frias19578162013-05-13 18:01:12 +000095/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
Fabio Estevam067a6592014-09-13 18:21:36 -030096static struct i2c_pads_info i2c_pad_info1 = {
Renato Frias19578162013-05-13 18:01:12 +000097 .scl = {
98 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
Eric Nelson10fda482013-11-04 17:00:51 -070099 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
Renato Frias19578162013-05-13 18:01:12 +0000100 .gp = IMX_GPIO_NR(2, 30)
101 },
102 .sda = {
103 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
Eric Nelson10fda482013-11-04 17:00:51 -0700104 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
Renato Frias19578162013-05-13 18:01:12 +0000105 .gp = IMX_GPIO_NR(4, 13)
106 }
107};
108
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200109#ifndef CONFIG_SYS_FLASH_CFI
Renato Frias19578162013-05-13 18:01:12 +0000110/*
111 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
112 * Compass Sensor, Accelerometer, Res Touch
113 */
Fabio Estevam067a6592014-09-13 18:21:36 -0300114static struct i2c_pads_info i2c_pad_info2 = {
Renato Frias19578162013-05-13 18:01:12 +0000115 .scl = {
116 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
Eric Nelson10fda482013-11-04 17:00:51 -0700117 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
Renato Frias19578162013-05-13 18:01:12 +0000118 .gp = IMX_GPIO_NR(1, 3)
119 },
120 .sda = {
121 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
Eric Nelson10fda482013-11-04 17:00:51 -0700122 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
Renato Frias19578162013-05-13 18:01:12 +0000123 .gp = IMX_GPIO_NR(3, 18)
124 }
125};
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200126#endif
Renato Frias19578162013-05-13 18:01:12 +0000127
Fabio Estevam067a6592014-09-13 18:21:36 -0300128static iomux_v3_cfg_t const i2c3_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700129 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
Renato Frias19578162013-05-13 18:01:12 +0000130};
131
Fabio Estevam067a6592014-09-13 18:21:36 -0300132static iomux_v3_cfg_t const port_exp[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700133 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
Renato Friasa1f67802013-05-13 18:01:13 +0000134};
135
Ye.Li8fe280f2014-10-30 18:53:49 +0800136/*Define for building port exp gpio, pin starts from 0*/
137#define PORTEXP_IO_NR(chip, pin) \
138 ((chip << 5) + pin)
139
140/*Get the chip addr from a ioexp gpio*/
141#define PORTEXP_IO_TO_CHIP(gpio_nr) \
142 (gpio_nr >> 5)
143
144/*Get the pin number from a ioexp gpio*/
145#define PORTEXP_IO_TO_PIN(gpio_nr) \
146 (gpio_nr & 0x1f)
147
148static int port_exp_direction_output(unsigned gpio, int value)
149{
150 int ret;
151
152 i2c_set_bus_num(2);
153 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
154 if (ret)
155 return ret;
156
157 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
158 (1 << PORTEXP_IO_TO_PIN(gpio)),
159 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
160
161 if (ret)
162 return ret;
163
164 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
165 (1 << PORTEXP_IO_TO_PIN(gpio)),
166 (value << PORTEXP_IO_TO_PIN(gpio)));
167
168 if (ret)
169 return ret;
170
171 return 0;
172}
173
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200174static iomux_v3_cfg_t const eimnor_pads[] = {
175 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
176 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
177 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
178 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
179 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
180 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
181 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
182 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
183 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
184 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
185 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
186 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
187 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
188 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
189 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
190 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
191 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
192 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
193 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
194 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
195 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
196 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
197 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
198 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
199 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
200 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
201 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
202 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
203 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
204 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
205 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
206 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
207 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
208 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
209 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
210 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
211 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
212 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
213 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
214 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
215 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
216 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
217 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
218};
219
220static void eimnor_cs_setup(void)
221{
222 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
223
224 writel(0x00020181, &weim_regs->cs0gcr1);
225 writel(0x00000001, &weim_regs->cs0gcr2);
226 writel(0x0a020000, &weim_regs->cs0rcr1);
227 writel(0x0000c000, &weim_regs->cs0rcr2);
228 writel(0x0804a240, &weim_regs->cs0wcr1);
229 writel(0x00000120, &weim_regs->wcr);
230
231 set_chipselect_size(CS0_128);
232}
233
234static void setup_iomux_eimnor(void)
235{
236 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
237
238 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
239
240 eimnor_cs_setup();
241}
242
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000243static void setup_iomux_enet(void)
244{
245 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
246}
247
Fabio Estevam067a6592014-09-13 18:21:36 -0300248static iomux_v3_cfg_t const usdhc3_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700249 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
Fabio Estevam7dd65452012-09-24 08:09:33 +0000261};
262
263static void setup_iomux_uart(void)
264{
265 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
266}
267
268#ifdef CONFIG_FSL_ESDHC
Fabio Estevam067a6592014-09-13 18:21:36 -0300269static struct fsl_esdhc_cfg usdhc_cfg[1] = {
Fabio Estevam7dd65452012-09-24 08:09:33 +0000270 {USDHC3_BASE_ADDR},
271};
272
273int board_mmc_getcd(struct mmc *mmc)
274{
275 gpio_direction_input(IMX_GPIO_NR(6, 15));
276 return !gpio_get_value(IMX_GPIO_NR(6, 15));
277}
278
279int board_mmc_init(bd_t *bis)
280{
281 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
282
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000283 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Fabio Estevam7dd65452012-09-24 08:09:33 +0000284 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
285}
286#endif
287
Ye.Li83bb3212014-11-12 14:02:05 +0800288#ifdef CONFIG_NAND_MXS
289static iomux_v3_cfg_t gpmi_pads[] = {
290 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
291 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
292 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
293 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
294 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
295 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
296 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
297 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
298 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
299 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
300 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
301 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
302 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
303 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
304 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
305 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
306};
307
308static void setup_gpmi_nand(void)
309{
310 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
311
312 /* config gpmi nand iomux */
313 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
314
Ye.Li5f22d882015-01-12 17:37:13 +0800315 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
Ye.Li83bb3212014-11-12 14:02:05 +0800316 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
Ye.Li5f22d882015-01-12 17:37:13 +0800317 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
Ye.Li83bb3212014-11-12 14:02:05 +0800318
319 /* enable apbh clock gating */
320 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
321}
322#endif
323
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000324int mx6_rgmii_rework(struct phy_device *phydev)
325{
326 unsigned short val;
327
328 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
329 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
330 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
331 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
332
333 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
334 val &= 0xffe3;
335 val |= 0x18;
336 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
337
338 /* introduce tx clock delay */
339 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
340 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
341 val |= 0x0100;
342 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
343
344 return 0;
345}
346
347int board_phy_config(struct phy_device *phydev)
348{
349 mx6_rgmii_rework(phydev);
350
351 if (phydev->drv->config)
352 phydev->drv->config(phydev);
353
354 return 0;
355}
356
Peng Fan361b7152015-07-11 11:38:47 +0800357static void setup_fec(void)
358{
359 if (is_mx6dqp()) {
360 /*
361 * select ENET MAC0 TX clock from PLL
362 */
363 imx_iomux_set_gpr_register(5, 9, 1, 1);
364 enable_fec_anatop_clock(ENET_125MHZ);
365 }
366
367 setup_iomux_enet();
368}
369
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000370int board_eth_init(bd_t *bis)
371{
Peng Fan361b7152015-07-11 11:38:47 +0800372 setup_fec();
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000373
Fabio Estevam579be2f2014-01-04 17:36:31 -0200374 return cpu_eth_init(bis);
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000375}
376
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000377#define BOARD_REV_B 0x200
378#define BOARD_REV_A 0x100
379
380static int mx6sabre_rev(void)
381{
382 /*
383 * Get Board ID information from OCOTP_GP1[15:8]
384 * i.MX6Q ARD RevA: 0x01
385 * i.MX6Q ARD RevB: 0x02
386 */
387 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
Benoît Thébaudeau8f3ff112013-04-23 10:17:38 +0000388 struct fuse_bank *bank = &ocotp->bank[4];
389 struct fuse_bank4_regs *fuse =
390 (struct fuse_bank4_regs *)bank->fuse_regs;
391 int reg = readl(&fuse->gp1);
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000392 int ret;
393
394 switch (reg >> 8 & 0x0F) {
395 case 0x02:
396 ret = BOARD_REV_B;
397 break;
398 case 0x01:
399 default:
400 ret = BOARD_REV_A;
401 break;
402 }
403
404 return ret;
405}
406
Fabio Estevam7dd65452012-09-24 08:09:33 +0000407u32 get_board_rev(void)
408{
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000409 int rev = mx6sabre_rev();
410
411 return (get_cpu_rev() & ~(0xF << 8)) | rev;
Fabio Estevam7dd65452012-09-24 08:09:33 +0000412}
413
Fabio Estevam510922a2014-09-22 13:55:52 -0300414#if defined(CONFIG_VIDEO_IPUV3)
415static void do_enable_hdmi(struct display_info_t const *dev)
416{
417 imx_enable_hdmi_phy();
418}
419
420struct display_info_t const displays[] = {{
421 .bus = -1,
422 .addr = 0,
423 .pixfmt = IPU_PIX_FMT_RGB24,
424 .detect = detect_hdmi,
425 .enable = do_enable_hdmi,
426 .mode = {
427 .name = "HDMI",
428 .refresh = 60,
429 .xres = 1024,
430 .yres = 768,
431 .pixclock = 15385,
432 .left_margin = 220,
433 .right_margin = 40,
434 .upper_margin = 21,
435 .lower_margin = 7,
436 .hsync_len = 60,
437 .vsync_len = 10,
438 .sync = FB_SYNC_EXT,
439 .vmode = FB_VMODE_NONINTERLACED,
440} } };
441size_t display_count = ARRAY_SIZE(displays);
442
443static void setup_display(void)
444{
445 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
446 int reg;
447
448 enable_ipu_clock();
449 imx_setup_hdmi();
450
451 reg = readl(&mxc_ccm->chsccdr);
452 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
453 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
454 writel(reg, &mxc_ccm->chsccdr);
455}
456#endif /* CONFIG_VIDEO_IPUV3 */
457
458/*
459 * Do not overwrite the console
460 * Use always serial for U-Boot console
461 */
462int overwrite_console(void)
463{
464 return 1;
465}
466
Fabio Estevam7dd65452012-09-24 08:09:33 +0000467int board_early_init_f(void)
468{
469 setup_iomux_uart();
Fabio Estevam510922a2014-09-22 13:55:52 -0300470#ifdef CONFIG_VIDEO_IPUV3
471 setup_display();
472#endif
Ye.Li83bb3212014-11-12 14:02:05 +0800473
474#ifdef CONFIG_NAND_MXS
475 setup_gpmi_nand();
476#endif
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200477
Fabio Estevam7dd65452012-09-24 08:09:33 +0000478 return 0;
479}
480
481int board_init(void)
482{
483 /* address of boot parameters */
484 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
485
Renato Frias19578162013-05-13 18:01:12 +0000486 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
487 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
488 /* I2C 3 Steer */
489 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
490 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200491#ifndef CONFIG_SYS_FLASH_CFI
Renato Frias19578162013-05-13 18:01:12 +0000492 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200493#endif
Renato Friasa1f67802013-05-13 18:01:13 +0000494 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
495 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
496
Fabio Estevamcdbdde32014-11-14 11:27:23 -0200497 setup_iomux_eimnor();
Fabio Estevam7dd65452012-09-24 08:09:33 +0000498 return 0;
499}
500
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300501#ifdef CONFIG_MXC_SPI
502int board_spi_cs_gpio(unsigned bus, unsigned cs)
503{
504 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
505}
506#endif
507
Ye.Li593243d2014-11-06 16:29:02 +0800508int power_init_board(void)
509{
510 struct pmic *p;
Peng Fan361b7152015-07-11 11:38:47 +0800511 unsigned int value;
Ye.Li593243d2014-11-06 16:29:02 +0800512
513 p = pfuze_common_init(I2C_PMIC);
514 if (!p)
515 return -ENODEV;
516
Peng Fan361b7152015-07-11 11:38:47 +0800517 if (is_mx6dqp()) {
518 /* set SW2 staby volatage 0.975V*/
519 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
520 value &= ~0x3f;
521 value |= 0x17;
522 pmic_reg_write(p, PFUZE100_SW2STBY, value);
523 }
Peng Fan258c98f2015-01-27 10:14:04 +0800524
Peng Fan361b7152015-07-11 11:38:47 +0800525 return pfuze_mode_init(p, APS_PFM);
Ye.Li593243d2014-11-06 16:29:02 +0800526}
527
Otavio Salvador85449db2013-03-16 08:05:07 +0000528#ifdef CONFIG_CMD_BMODE
529static const struct boot_mode board_boot_modes[] = {
530 /* 4 bit bus width */
531 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
532 {NULL, 0},
533};
534#endif
535
536int board_late_init(void)
537{
538#ifdef CONFIG_CMD_BMODE
539 add_board_boot_modes(board_boot_modes);
540#endif
541
Peng Fane6fc8992015-07-11 11:38:46 +0800542#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
543 setenv("board_name", "SABREAUTO");
544
Peng Fan361b7152015-07-11 11:38:47 +0800545 if (is_mx6dqp())
546 setenv("board_rev", "MX6QP");
547 else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
Peng Fane6fc8992015-07-11 11:38:46 +0800548 setenv("board_rev", "MX6Q");
549 else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
550 setenv("board_rev", "MX6DL");
551#endif
552
Otavio Salvador85449db2013-03-16 08:05:07 +0000553 return 0;
554}
555
Fabio Estevam7dd65452012-09-24 08:09:33 +0000556int checkboard(void)
557{
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000558 int rev = mx6sabre_rev();
559 char *revname;
560
561 switch (rev) {
562 case BOARD_REV_B:
563 revname = "B";
564 break;
565 case BOARD_REV_A:
566 default:
567 revname = "A";
568 break;
569 }
570
571 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
Fabio Estevam7dd65452012-09-24 08:09:33 +0000572
573 return 0;
574}
Ye.Li8fe280f2014-10-30 18:53:49 +0800575
576#ifdef CONFIG_USB_EHCI_MX6
577#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
578#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
579
580iomux_v3_cfg_t const usb_otg_pads[] = {
581 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
582};
583
584int board_ehci_hcd_init(int port)
585{
586 switch (port) {
587 case 0:
588 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
589 ARRAY_SIZE(usb_otg_pads));
590
591 /*
592 * Set daisy chain for otg_pin_id on 6q.
593 * For 6dl, this bit is reserved.
594 */
595 imx_iomux_set_gpr_register(1, 13, 1, 0);
596 break;
597 case 1:
598 break;
599 default:
600 printf("MXC USB port %d not yet supported\n", port);
601 return -EINVAL;
602 }
603 return 0;
604}
605
606int board_ehci_power(int port, int on)
607{
608 switch (port) {
609 case 0:
610 if (on)
611 port_exp_direction_output(USB_OTG_PWR, 1);
612 else
613 port_exp_direction_output(USB_OTG_PWR, 0);
614 break;
615 case 1:
616 if (on)
617 port_exp_direction_output(USB_HOST1_PWR, 1);
618 else
619 port_exp_direction_output(USB_HOST1_PWR, 0);
620 break;
621 default:
622 printf("MXC USB port %d not yet supported\n", port);
623 return -EINVAL;
624 }
625
626 return 0;
627}
628#endif