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Nobuhiro Iwamatsu2a57e7e2012-01-11 10:45:01 +09001/*
2 * (C) Copyright 2008, 2011 Renesas Solutions Corp.
3 *
4 * SH7734 Internal I/O register
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu2a57e7e2012-01-11 10:45:01 +09007 */
8
9#ifndef _ASM_CPU_SH7734_H_
10#define _ASM_CPU_SH7734_H_
11
12#define CCR 0xFF00001C
13
14#define CACHE_OC_NUM_WAYS 4
15#define CCR_CACHE_INIT 0x0000090d
16
17/* SCIF */
18#define SCIF0_BASE 0xFFE40000
19#define SCIF1_BASE 0xFFE41000
20#define SCIF2_BASE 0xFFE42000
21#define SCIF3_BASE 0xFFE43000
22#define SCIF4_BASE 0xFFE44000
23#define SCIF5_BASE 0xFFE45000
24
25/* Timer */
Nobuhiro Iwamatsu73f35e02012-08-21 13:14:46 +090026#define TMU_BASE 0xFFD80000
Nobuhiro Iwamatsu2a57e7e2012-01-11 10:45:01 +090027
Nobuhiro Iwamatsu4eb0b782012-05-09 16:00:01 +090028/* PFC */
29#define PMMR (0xFFFC0000)
30#define MODESEL0 (0xFFFC004C)
31#define MODESEL2 (MODESEL0 + 0x4)
32#define MODESEL2_INIT (0x00003000)
33
34#define IPSR0 (0xFFFC001C)
35#define IPSR1 (IPSR0 + 0x4)
36#define IPSR2 (IPSR0 + 0x8)
37#define IPSR3 (IPSR0 + 0xC)
38#define IPSR4 (IPSR0 + 0x10)
39#define IPSR5 (IPSR0 + 0x14)
40#define IPSR6 (IPSR0 + 0x18)
41#define IPSR7 (IPSR0 + 0x1C)
42#define IPSR8 (IPSR0 + 0x20)
43#define IPSR9 (IPSR0 + 0x24)
44#define IPSR10 (IPSR0 + 0x28)
45#define IPSR11 (IPSR0 + 0x2C)
46
47#define GPSR0 (0xFFFC0004)
48#define GPSR1 (GPSR0 + 0x4)
49#define GPSR2 (GPSR0 + 0x8)
50#define GPSR3 (GPSR0 + 0xC)
51#define GPSR4 (GPSR0 + 0x10)
52#define GPSR5 (GPSR0 + 0x14)
53
54
Nobuhiro Iwamatsu2a57e7e2012-01-11 10:45:01 +090055#endif /* _ASM_CPU_SH7734_H_ */