| Andre Schwarz | 7fb3e7a | 2011-04-14 15:11:44 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Matrix Vision GmbH |
| 3 | * Andre Schwarz <andre.schwarz@matrix-vision.de> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __MERGERBOX_H__ |
| 15 | #define __MERGERBOX_H__ |
| 16 | |
| 17 | #define MV_GPIO |
| 18 | |
| 19 | /* |
| 20 | * GPIO Bank 1 |
| 21 | */ |
| 22 | #define TFT_SPI_EN (0x80000000>>0) |
| 23 | #define FPGA_CONFIG (0x80000000>>1) |
| 24 | #define FPGA_STATUS (0x80000000>>2) |
| 25 | #define FPGA_CONF_DONE (0x80000000>>3) |
| 26 | #define FPGA_DIN (0x80000000>>4) |
| 27 | #define FPGA_CCLK (0x80000000>>5) |
| 28 | #define MAN_RST (0x80000000>>6) |
| 29 | #define FPGA_SYS_RST (0x80000000>>7) |
| 30 | #define WD_WDI (0x80000000>>8) |
| 31 | #define TFT_RST (0x80000000>>9) |
| 32 | #define HISCON_GPIO1 (0x80000000>>10) |
| 33 | #define HISCON_GPIO2 (0x80000000>>11) |
| 34 | #define B2B_GPIO2 (0x80000000>>12) |
| 35 | #define CCU_GPIN (0x80000000>>13) |
| 36 | #define CCU_GPOUT (0x80000000>>14) |
| 37 | #define TFT_GPIO0 (0x80000000>>15) |
| 38 | #define TFT_GPIO1 (0x80000000>>16) |
| 39 | #define TFT_GPIO2 (0x80000000>>17) |
| 40 | #define TFT_GPIO3 (0x80000000>>18) |
| 41 | #define B2B_GPIO0 (0x80000000>>19) |
| 42 | #define B2B_GPIO1 (0x80000000>>20) |
| 43 | #define TFT_SPI_CPLD_CS (0x80000000>>21) |
| 44 | #define TFT_SPI_CS (0x80000000>>22) |
| 45 | #define CCU_PWR_EN (0x80000000>>23) |
| 46 | #define B2B_GPIO3 (0x80000000>>24) |
| 47 | #define CCU_PWR_STAT (0x80000000>>25) |
| 48 | |
| 49 | #define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) |
| 50 | #define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ |
| 51 | TFT_SPI_CPLD_CS) |
| 52 | #define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) |
| 53 | |
| 54 | /* |
| 55 | * GPIO Bank 2 |
| 56 | */ |
| 57 | #define SPI_FLASH_WP (0x80000000>>10) |
| 58 | #define SYS_EEPROM_WP (0x80000000>>11) |
| 59 | #define SPI_FLASH_CS (0x80000000>>22) |
| 60 | |
| 61 | #define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) |
| 62 | #define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) |
| 63 | #define MV_GPIO2_ODE 0 |
| 64 | |
| 65 | void mergerbox_tft_dim(u16 value); |
| 66 | |
| 67 | #endif |