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Stefan Roese17f50f222005-08-04 17:09:16 +02001/*
2 * (C) Copyright 2004-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
6 * Add support for Am29F016D and dynamic switch setting.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * Modified 4/5/2001
29 * Wait for completion of each sector erase command issued
30 * 4/5/2001
31 * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
32 */
33
34#include <common.h>
35#include <ppc4xx.h>
36#include <asm/processor.h>
37#include <ppc440.h>
38#include "bamboo.h"
39
40#undef DEBUG
41
42#ifdef DEBUG
43#define DEBUGF(x...) printf(x)
44#else
45#define DEBUGF(x...)
46#endif /* DEBUG */
47
48flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
49
50/*
51 * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
52 */
Stefan Roesec57c7982005-08-11 17:56:56 +020053static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
Stefan Roese17f50f222005-08-04 17:09:16 +020054 {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
55 {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
Stefan Roesea471db02007-06-01 15:19:29 +020056 {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
Stefan Roesec57c7982005-08-11 17:56:56 +020057 {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
58 {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
Stefan Roese17f50f222005-08-04 17:09:16 +020059 {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
60 {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
61 {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
Stefan Roesec57c7982005-08-11 17:56:56 +020062 {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
Stefan Roese17f50f222005-08-04 17:09:16 +020063};
64
65/*
66 * include common flash code (for amcc boards)
67 */
68#include "../common/flash.c"
69
70/*-----------------------------------------------------------------------
71 * Functions
72 */
73static ulong flash_get_size(vu_long * addr, flash_info_t * info);
74static int write_word(flash_info_t * info, ulong dest, ulong data);
75
76/*-----------------------------------------------------------------------
77 */
78
79unsigned long flash_init(void)
80{
81 unsigned long total_b = 0;
82 unsigned long size_b[CFG_MAX_FLASH_BANKS];
83 unsigned short index = 0;
84 int i;
85 unsigned long val;
86 unsigned long ebc_boot_size;
87 unsigned long boot_selection;
88
89 mfsdr(sdr_pstrp0, val);
90 index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
91
92 if ((index == 5) || (index == 7)) {
93 /*
94 * Boot Settings in IIC EEprom address 0xA8 or 0xA4
95 * Read Serial Device Strap Register1 in PPC440EP
96 */
97 mfsdr(sdr_sdstp1, val);
98 boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
99 ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
100
101 switch(boot_selection) {
102 case SDR0_SDSTP1_BOOT_SEL_EBC:
103 switch(ebc_boot_size) {
104 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
105 index = 3;
106 break;
107 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
108 index = 0;
109 break;
110 }
111 break;
112
113 case SDR0_SDSTP1_BOOT_SEL_PCI:
114 index = 1;
115 break;
116
117 case SDR0_SDSTP1_BOOT_SEL_NDFC:
118 index = 2;
119 break;
120 }
Stefan Roesec57c7982005-08-11 17:56:56 +0200121 } else if (index == 0) {
122 if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
123 index = 8; /* sram below op code flash -> new index 8 */
124 }
Stefan Roese17f50f222005-08-04 17:09:16 +0200125 }
126
127 DEBUGF("\n");
128 DEBUGF("FLASH: Index: %d\n", index);
129
130 /* Init: no FLASHes known */
131 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
132 flash_info[i].flash_id = FLASH_UNKNOWN;
133 flash_info[i].sector_count = -1;
134 flash_info[i].size = 0;
135
136 /* check whether the address is 0 */
Stefan Roesea471db02007-06-01 15:19:29 +0200137 if (flash_addr_table[index][i] == 0)
Stefan Roese17f50f222005-08-04 17:09:16 +0200138 continue;
Stefan Roese17f50f222005-08-04 17:09:16 +0200139
Stefan Roesea471db02007-06-01 15:19:29 +0200140 DEBUGF("Detection bank %d...\n", i);
Stefan Roese17f50f222005-08-04 17:09:16 +0200141 /* call flash_get_size() to initialize sector address */
142 size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
143 &flash_info[i]);
144 flash_info[i].size = size_b[i];
145 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
146 printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
147 i, size_b[i], size_b[i] << 20);
148 flash_info[i].sector_count = -1;
149 flash_info[i].size = 0;
150 }
151
152 /* Monitor protection ON by default */
153 (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
154 CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
155 &flash_info[i]);
156#if defined(CFG_ENV_IS_IN_FLASH)
157 (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
158 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
159 &flash_info[i]);
160#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
161 (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
162 CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
163 &flash_info[i]);
164#endif
165#endif
166
167 total_b += flash_info[i].size;
168 }
169
170 return total_b;
171}