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Aneesh V2c451f72011-06-16 23:30:47 +00001/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Aneesh V2c451f72011-06-16 23:30:47 +00007 */
8#ifndef ARMV7_H
9#define ARMV7_H
Aneesh V2c451f72011-06-16 23:30:47 +000010
Aneesh Vad577c82011-07-21 09:10:04 -040011/* Cortex-A9 revisions */
12#define MIDR_CORTEX_A9_R0P1 0x410FC091
13#define MIDR_CORTEX_A9_R1P2 0x411FC092
14#define MIDR_CORTEX_A9_R1P3 0x411FC093
Aneesh V5ab12a92011-07-21 09:29:23 -040015#define MIDR_CORTEX_A9_R2P10 0x412FC09A
Aneesh Vad577c82011-07-21 09:10:04 -040016
Sricharan508a58f2011-11-15 09:49:55 -050017/* Cortex-A15 revisions */
18#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
SRICHARAN Reed7c0f2013-02-12 01:33:41 +000019#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
Sricharan508a58f2011-11-15 09:49:55 -050020
Andre Przywara16212b52013-09-19 18:06:41 +020021/* Cortex-A7 revisions */
22#define MIDR_CORTEX_A7_R0P0 0x410FC070
23
24#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
25
26/* ID_PFR1 feature fields */
27#define CPUID_ARM_SEC_SHIFT 4
28#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
29#define CPUID_ARM_VIRT_SHIFT 12
30#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
31#define CPUID_ARM_GENTIMER_SHIFT 16
32#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
33
34/* valid bits in CBAR register / PERIPHBASE value */
35#define CBAR_MASK 0xFFFF8000
36
Aneesh V2c451f72011-06-16 23:30:47 +000037/* CCSIDR */
38#define CCSIDR_LINE_SIZE_OFFSET 0
39#define CCSIDR_LINE_SIZE_MASK 0x7
40#define CCSIDR_ASSOCIATIVITY_OFFSET 3
41#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
42#define CCSIDR_NUM_SETS_OFFSET 13
43#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
44
45/*
46 * Values for InD field in CSSELR
47 * Selects the type of cache
48 */
49#define ARMV7_CSSELR_IND_DATA_UNIFIED 0
50#define ARMV7_CSSELR_IND_INSTRUCTION 1
51
52/* Values for Ctype fields in CLIDR */
53#define ARMV7_CLIDR_CTYPE_NO_CACHE 0
54#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
55#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
56#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
57#define ARMV7_CLIDR_CTYPE_UNIFIED 4
58
Andre Przywarad75ba502013-09-19 18:06:39 +020059#ifndef __ASSEMBLY__
60#include <linux/types.h>
61
Aneesh V2c451f72011-06-16 23:30:47 +000062/*
63 * CP15 Barrier instructions
64 * Please note that we have separate barrier instructions in ARMv7
65 * However, we use the CP15 based instructtions because we use
66 * -march=armv5 in U-Boot
67 */
68#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
69#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
70#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
71
72void v7_outer_cache_enable(void);
73void v7_outer_cache_disable(void);
74void v7_outer_cache_flush_all(void);
75void v7_outer_cache_inval_all(void);
76void v7_outer_cache_flush_range(u32 start, u32 end);
77void v7_outer_cache_inval_range(u32 start, u32 end);
78
Andre Przywarad4296882013-09-19 18:06:45 +020079#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
Andre Przywara1ef92382013-09-19 18:06:42 +020080
81int armv7_switch_nonsec(void);
Andre Przywarad4296882013-09-19 18:06:45 +020082int armv7_switch_hyp(void);
Andre Przywara1ef92382013-09-19 18:06:42 +020083
Andre Przywara16212b52013-09-19 18:06:41 +020084/* defined in assembly file */
85unsigned int _nonsec_init(void);
Andre Przywaraba6a1692013-09-19 18:06:44 +020086void _smp_pen(void);
Andre Przywarad4296882013-09-19 18:06:45 +020087void _switch_to_hyp(void);
88#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
Andre Przywara16212b52013-09-19 18:06:41 +020089
Andre Przywarad75ba502013-09-19 18:06:39 +020090#endif /* ! __ASSEMBLY__ */
91
Aneesh V2c451f72011-06-16 23:30:47 +000092#endif