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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simek1f4f3d32016-04-07 15:58:23 +02002/*
3 * Configuration for Xilinx ZynqMP zcu102
4 *
5 * (C) Copyright 2015 Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
Michal Simek1f4f3d32016-04-07 15:58:23 +02007 */
8
9#ifndef __CONFIG_ZYNQMP_ZCU102_H
10#define __CONFIG_ZYNQMP_ZCU102_H
11
12#define CONFIG_ZYNQ_SDHCI1
Michal Simek1f4f3d32016-04-07 15:58:23 +020013#define CONFIG_SYS_I2C_MAX_HOPS 1
14#define CONFIG_SYS_NUM_I2C_BUSES 18
15#define CONFIG_SYS_I2C_BUSES { \
16 {0, {I2C_NULL_HOP} }, \
17 {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
18 {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
19 {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
20 {1, {I2C_NULL_HOP} }, \
21 {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
22 {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
23 {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
24 {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
25 {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
26 {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
27 {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
28 {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
29 {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
30 {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
31 {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
32 {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
33 {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
34 }
35
Michal Simekff9bd8e2016-04-11 13:48:32 +020036#define CONFIG_PCA953X
Michal Simekff9bd8e2016-04-11 13:48:32 +020037
Michal Simek6919b4b2016-04-22 11:48:49 +020038#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Michal Simek6919b4b2016-04-22 11:48:49 +020039#define CONFIG_ZYNQ_EEPROM_BUS 5
40#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
Michal Simek6919b4b2016-04-22 11:48:49 +020041
Michal Simek343671e2018-06-04 08:27:50 +020042#define CONFIG_SPD_EEPROM
43#define CONFIG_DDR_SPD
44
Michal Simek1f4f3d32016-04-07 15:58:23 +020045#include <configs/xilinx_zynqmp.h>
46
47#endif /* __CONFIG_ZYNQMP_ZCU102_H */