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gerrit.cesnet.cz / github / trini / u-boot / 3345d18d5baad05807ecac36bc4125dbc74d288f / . / arch / powerpc / cpu / mpc85xx / t1040_serdes.c
blob: d86bb2737246201e14a63508f2a6c8b3ab0b4015 [file] [log] [blame]
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]11
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]12
13static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]15 PCIE2, PCIE2, PCIE2, PCIE2},
16 [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
17 PCIE2, PCIE3, PCIE4, SATA1},
18 [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
19 PCIE2, PCIE3, SATA2, SATA1},
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]20 [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
21 PCIE2, PCIE2, PCIE2, PCIE2},
22 [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
23 PCIE2, PCIE2, PCIE2, PCIE2},
24 [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
25 PCIE2, PCIE3, PCIE4, SATA1},
26 [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
27 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
28 [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
29 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
30 [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
31 PCIE2, PCIE3, PCIE4, SATA1},
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]32 [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
33 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]34 [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
35 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
36 [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
37 PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
38 [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
39 PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
40 [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
41 AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]42 [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
43 PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]44 [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
45 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
46 [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
47 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]48};
49
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]50enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
51{
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]52 return serdes_cfg_tbl[cfg][lane];
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]53}
54
55int is_serdes_prtcl_valid(int serdes, u32 prtcl)
56{
57 int i;
58
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]59 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]60 return 0;
61
62 for (i = 0; i < SRDS_MAX_LANES; i++) {
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]63 if (serdes_cfg_tbl[prtcl][i] != NONE)
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]64 return 1;
65 }
66
67 return 0;
68}