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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
Wolfgang Denk8cba0902006-05-12 16:15:46 +02005 * (C) Copyright 2000-2006
wdenkd4ca31c2004-01-02 14:00:00 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
wdenkfe8c2802002-11-03 00:38:21 +00008 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
13 * are needed. -- Dan
14 *
wdenkfe8c2802002-11-03 00:38:21 +000015 */
16#ifndef __CPM_8XX__
17#define __CPM_8XX__
18
wdenkfe8c2802002-11-03 00:38:21 +000019#include <asm/8xx_immap.h>
20
21/* CPM Command register.
22*/
wdenk7c7a23b2002-12-07 00:20:59 +000023#define CPM_CR_RST ((ushort)0x8000)
24#define CPM_CR_OPCODE ((ushort)0x0f00)
25#define CPM_CR_CHAN ((ushort)0x00f0)
26#define CPM_CR_FLG ((ushort)0x0001)
wdenkfe8c2802002-11-03 00:38:21 +000027
28/* Some commands (there are more...later)
29*/
30#define CPM_CR_INIT_TRX ((ushort)0x0000)
31#define CPM_CR_INIT_RX ((ushort)0x0001)
32#define CPM_CR_INIT_TX ((ushort)0x0002)
33#define CPM_CR_HUNT_MODE ((ushort)0x0003)
34#define CPM_CR_STOP_TX ((ushort)0x0004)
35#define CPM_CR_RESTART_TX ((ushort)0x0006)
36#define CPM_CR_SET_GADDR ((ushort)0x0008)
37
38/* Channel numbers.
39*/
wdenk7c7a23b2002-12-07 00:20:59 +000040#define CPM_CR_CH_SCC1 ((ushort)0x0000)
41#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
42#define CPM_CR_CH_SCC2 ((ushort)0x0004)
43#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
44#define CPM_CR_CH_SCC3 ((ushort)0x0008)
45#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
46#define CPM_CR_CH_SCC4 ((ushort)0x000c)
47#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
wdenkfe8c2802002-11-03 00:38:21 +000048
49#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
50
51/*
52 * DPRAM defines and allocation functions
53 */
54
55/* The dual ported RAM is multi-functional. Some areas can be (and are
56 * being) used for microcode. There is an area that can only be used
57 * as data ram for buffer descriptors, which is all we use right now.
58 * Currently the first 512 and last 256 bytes are used for microcode.
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#ifdef CONFIG_SYS_ALLOC_DPRAM
wdenkfe8c2802002-11-03 00:38:21 +000061
62#define CPM_DATAONLY_BASE ((uint)0x0800)
63#define CPM_DATAONLY_SIZE ((uint)0x0700)
64#define CPM_DP_NOSPACE ((uint)0x7fffffff)
65
66#else
67
68#define CPM_SERIAL_BASE 0x0800
69#define CPM_I2C_BASE 0x0820
70#define CPM_SPI_BASE 0x0840
71#define CPM_FEC_BASE 0x0860
wdenk79536a62004-09-27 20:20:11 +000072#define CPM_SERIAL2_BASE 0x08E0
wdenkfe8c2802002-11-03 00:38:21 +000073#define CPM_SCC_BASE 0x0900
74#define CPM_POST_BASE 0x0980
wdenk281e00a2004-08-01 22:48:16 +000075#define CPM_WLKBD_BASE 0x0a00
wdenkfe8c2802002-11-03 00:38:21 +000076
77#endif
78
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
wdenkfe8c2802002-11-03 00:38:21 +000080#define CPM_POST_WORD_ADDR 0x07FC
wdenkea909b72002-11-21 23:11:29 +000081#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
wdenkea909b72002-11-21 23:11:29 +000083#endif
wdenkfe8c2802002-11-03 00:38:21 +000084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
wdenkbdccc4f2003-08-05 17:43:17 +000086#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
87#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
wdenkbdccc4f2003-08-05 17:43:17 +000089#endif
90
wdenkfe8c2802002-11-03 00:38:21 +000091#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
92
93/* Export the base address of the communication processor registers
94 * and dual port ram.
95 */
96extern cpm8xx_t *cpmp; /* Pointer to comm processor */
97
98/* Buffer descriptors used by many of the CPM protocols.
99*/
100typedef struct cpm_buf_desc {
101 ushort cbd_sc; /* Status and Control */
102 ushort cbd_datlen; /* Data length in buffer */
103 uint cbd_bufaddr; /* Buffer address in host memory */
104} cbd_t;
105
Mike Williams16263082011-07-22 04:01:30 +0000106#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
wdenkfe8c2802002-11-03 00:38:21 +0000107#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
108#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
109#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
110#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
111#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
112#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
113#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
114#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
115#define BD_SC_BR ((ushort)0x0020) /* Break received */
116#define BD_SC_FR ((ushort)0x0010) /* Framing error */
117#define BD_SC_PR ((ushort)0x0008) /* Parity error */
118#define BD_SC_OV ((ushort)0x0002) /* Overrun */
119#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
120
121/* Parameter RAM offsets.
122*/
123#define PROFF_SCC1 ((uint)0x0000)
124#define PROFF_IIC ((uint)0x0080)
Scott Wooda166fbc2013-05-17 20:01:54 -0500125#define PROFF_REVNUM ((uint)0x00b0)
wdenkfe8c2802002-11-03 00:38:21 +0000126#define PROFF_SCC2 ((uint)0x0100)
127#define PROFF_SPI ((uint)0x0180)
128#define PROFF_SCC3 ((uint)0x0200)
129#define PROFF_SMC1 ((uint)0x0280)
130#define PROFF_SCC4 ((uint)0x0300)
131#define PROFF_SMC2 ((uint)0x0380)
132
133/* Define enough so I can at least use the serial port as a UART.
wdenkfe8c2802002-11-03 00:38:21 +0000134 */
135typedef struct smc_uart {
136 ushort smc_rbase; /* Rx Buffer descriptor base address */
137 ushort smc_tbase; /* Tx Buffer descriptor base address */
138 u_char smc_rfcr; /* Rx function code */
139 u_char smc_tfcr; /* Tx function code */
140 ushort smc_mrblr; /* Max receive buffer length */
141 uint smc_rstate; /* Internal */
142 uint smc_idp; /* Internal */
143 ushort smc_rbptr; /* Internal */
144 ushort smc_ibc; /* Internal */
145 uint smc_rxtmp; /* Internal */
146 uint smc_tstate; /* Internal */
147 uint smc_tdp; /* Internal */
148 ushort smc_tbptr; /* Internal */
149 ushort smc_tbc; /* Internal */
150 uint smc_txtmp; /* Internal */
151 ushort smc_maxidl; /* Maximum idle characters */
152 ushort smc_tmpidl; /* Temporary idle counter */
153 ushort smc_brklen; /* Last received break length */
154 ushort smc_brkec; /* rcv'd break condition counter */
155 ushort smc_brkcr; /* xmt break count register */
156 ushort smc_rmask; /* Temporary bit mask */
Heiko Schocherb423d052008-01-11 01:12:07 +0100157 u_char res1[8];
158 ushort smc_rpbase; /* Relocation pointer */
wdenkfe8c2802002-11-03 00:38:21 +0000159} smc_uart_t;
160
161/* Function code bits.
162*/
163#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
164
165/* SMC uart mode register.
166*/
167#define SMCMR_REN ((ushort)0x0001)
168#define SMCMR_TEN ((ushort)0x0002)
169#define SMCMR_DM ((ushort)0x000c)
170#define SMCMR_SM_GCI ((ushort)0x0000)
171#define SMCMR_SM_UART ((ushort)0x0020)
172#define SMCMR_SM_TRANS ((ushort)0x0030)
173#define SMCMR_SM_MASK ((ushort)0x0030)
174#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
175#define SMCMR_REVD SMCMR_PM_EVEN
176#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
177#define SMCMR_BS SMCMR_PEN
178#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
179#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
180#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
181
182/* SMC2 as Centronics parallel printer. It is half duplex, in that
183 * it can only receive or transmit. The parameter ram values for
184 * each direction are either unique or properly overlap, so we can
185 * include them in one structure.
186 */
187typedef struct smc_centronics {
188 ushort scent_rbase;
189 ushort scent_tbase;
190 u_char scent_cfcr;
191 u_char scent_smask;
192 ushort scent_mrblr;
193 uint scent_rstate;
194 uint scent_r_ptr;
195 ushort scent_rbptr;
196 ushort scent_r_cnt;
197 uint scent_rtemp;
198 uint scent_tstate;
199 uint scent_t_ptr;
200 ushort scent_tbptr;
201 ushort scent_t_cnt;
202 uint scent_ttemp;
203 ushort scent_max_sl;
204 ushort scent_sl_cnt;
205 ushort scent_character1;
206 ushort scent_character2;
207 ushort scent_character3;
208 ushort scent_character4;
209 ushort scent_character5;
210 ushort scent_character6;
211 ushort scent_character7;
212 ushort scent_character8;
213 ushort scent_rccm;
214 ushort scent_rccr;
215} smc_cent_t;
216
217/* Centronics Status Mask Register.
218*/
219#define SMC_CENT_F ((u_char)0x08)
220#define SMC_CENT_PE ((u_char)0x04)
221#define SMC_CENT_S ((u_char)0x02)
222
223/* SMC Event and Mask register.
224*/
225#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
226#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
227#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
228#define SMCM_BSY ((unsigned char)0x04)
229#define SMCM_TX ((unsigned char)0x02)
230#define SMCM_RX ((unsigned char)0x01)
231
232/* Baud rate generators.
233*/
234#define CPM_BRG_RST ((uint)0x00020000)
235#define CPM_BRG_EN ((uint)0x00010000)
236#define CPM_BRG_EXTC_INT ((uint)0x00000000)
237#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
238#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
239#define CPM_BRG_ATB ((uint)0x00002000)
240#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
241#define CPM_BRG_DIV16 ((uint)0x00000001)
242
243/* SI Clock Route Register
244*/
245#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
246#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
247#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
248#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
249#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
250#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
251#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
252#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
253
254/* SCCs.
255*/
256#define SCC_GSMRH_IRP ((uint)0x00040000)
257#define SCC_GSMRH_GDE ((uint)0x00010000)
258#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
259#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
260#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
261#define SCC_GSMRH_REVD ((uint)0x00002000)
262#define SCC_GSMRH_TRX ((uint)0x00001000)
263#define SCC_GSMRH_TTX ((uint)0x00000800)
264#define SCC_GSMRH_CDP ((uint)0x00000400)
265#define SCC_GSMRH_CTSP ((uint)0x00000200)
266#define SCC_GSMRH_CDS ((uint)0x00000100)
267#define SCC_GSMRH_CTSS ((uint)0x00000080)
268#define SCC_GSMRH_TFL ((uint)0x00000040)
269#define SCC_GSMRH_RFW ((uint)0x00000020)
270#define SCC_GSMRH_TXSY ((uint)0x00000010)
271#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
272#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
273#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
274#define SCC_GSMRH_RTSM ((uint)0x00000002)
275#define SCC_GSMRH_RSYN ((uint)0x00000001)
276
277#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
278#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
279#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
280#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
281#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
282#define SCC_GSMRL_TCI ((uint)0x10000000)
283#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
284#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
285#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
286#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
287#define SCC_GSMRL_RINV ((uint)0x02000000)
288#define SCC_GSMRL_TINV ((uint)0x01000000)
289#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
290#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
291#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
292#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
293#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
294#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
295#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
296#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
297#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
298#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
299#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
300#define SCC_GSMRL_TEND ((uint)0x00040000)
301#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
302#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
303#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
304#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
305#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
306#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
307#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
308#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
309#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
310#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
311#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
312#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
313#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
314#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
315#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
316#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
317#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
318#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
319#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
320#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
321#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
322#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
323#define SCC_GSMRL_ENR ((uint)0x00000020)
324#define SCC_GSMRL_ENT ((uint)0x00000010)
325#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
326#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
327#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
328#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
329#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
330#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
331#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
332#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
333#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
334#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
335
336#define SCC_TODR_TOD ((ushort)0x8000)
337
338/* SCC Event and Mask register.
339*/
340#define SCCM_TXE ((unsigned char)0x10)
341#define SCCM_BSY ((unsigned char)0x04)
342#define SCCM_TX ((unsigned char)0x02)
343#define SCCM_RX ((unsigned char)0x01)
344
345typedef struct scc_param {
346 ushort scc_rbase; /* Rx Buffer descriptor base address */
347 ushort scc_tbase; /* Tx Buffer descriptor base address */
348 u_char scc_rfcr; /* Rx function code */
349 u_char scc_tfcr; /* Tx function code */
350 ushort scc_mrblr; /* Max receive buffer length */
351 uint scc_rstate; /* Internal */
352 uint scc_idp; /* Internal */
353 ushort scc_rbptr; /* Internal */
354 ushort scc_ibc; /* Internal */
355 uint scc_rxtmp; /* Internal */
356 uint scc_tstate; /* Internal */
357 uint scc_tdp; /* Internal */
358 ushort scc_tbptr; /* Internal */
359 ushort scc_tbc; /* Internal */
360 uint scc_txtmp; /* Internal */
361 uint scc_rcrc; /* Internal */
362 uint scc_tcrc; /* Internal */
363} sccp_t;
364
365/* Function code bits.
366*/
367#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
368
369/* CPM Ethernet through SCCx.
370 */
371typedef struct scc_enet {
372 sccp_t sen_genscc;
373 uint sen_cpres; /* Preset CRC */
374 uint sen_cmask; /* Constant mask for CRC */
375 uint sen_crcec; /* CRC Error counter */
376 uint sen_alec; /* alignment error counter */
377 uint sen_disfc; /* discard frame counter */
378 ushort sen_pads; /* Tx short frame pad character */
379 ushort sen_retlim; /* Retry limit threshold */
380 ushort sen_retcnt; /* Retry limit counter */
381 ushort sen_maxflr; /* maximum frame length register */
382 ushort sen_minflr; /* minimum frame length register */
383 ushort sen_maxd1; /* maximum DMA1 length */
384 ushort sen_maxd2; /* maximum DMA2 length */
385 ushort sen_maxd; /* Rx max DMA */
386 ushort sen_dmacnt; /* Rx DMA counter */
387 ushort sen_maxb; /* Max BD byte count */
388 ushort sen_gaddr1; /* Group address filter */
389 ushort sen_gaddr2;
390 ushort sen_gaddr3;
391 ushort sen_gaddr4;
392 uint sen_tbuf0data0; /* Save area 0 - current frame */
393 uint sen_tbuf0data1; /* Save area 1 - current frame */
394 uint sen_tbuf0rba; /* Internal */
395 uint sen_tbuf0crc; /* Internal */
396 ushort sen_tbuf0bcnt; /* Internal */
397 ushort sen_paddrh; /* physical address (MSB) */
398 ushort sen_paddrm;
399 ushort sen_paddrl; /* physical address (LSB) */
400 ushort sen_pper; /* persistence */
401 ushort sen_rfbdptr; /* Rx first BD pointer */
402 ushort sen_tfbdptr; /* Tx first BD pointer */
403 ushort sen_tlbdptr; /* Tx last BD pointer */
404 uint sen_tbuf1data0; /* Save area 0 - current frame */
405 uint sen_tbuf1data1; /* Save area 1 - current frame */
406 uint sen_tbuf1rba; /* Internal */
407 uint sen_tbuf1crc; /* Internal */
408 ushort sen_tbuf1bcnt; /* Internal */
409 ushort sen_txlen; /* Tx Frame length counter */
410 ushort sen_iaddr1; /* Individual address filter */
411 ushort sen_iaddr2;
412 ushort sen_iaddr3;
413 ushort sen_iaddr4;
414 ushort sen_boffcnt; /* Backoff counter */
415
416 /* NOTE: Some versions of the manual have the following items
417 * incorrectly documented. Below is the proper order.
418 */
419 ushort sen_taddrh; /* temp address (MSB) */
420 ushort sen_taddrm;
421 ushort sen_taddrl; /* temp address (LSB) */
422} scc_enet_t;
423
424/**********************************************************************
425 *
426 * Board specific configuration settings.
427 *
428 * Please note that we use the presence of a #define SCC_ENET and/or
429 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
430 **********************************************************************/
431
wdenkfe8c2802002-11-03 00:38:21 +0000432/*** BSEIP **********************************************************/
433
434#ifdef CONFIG_BSEIP
435/* This ENET stuff is for the MPC823 with ethernet on SCC2.
436 * This is unique to the BSE ip-Engine board.
437 */
438#define PROFF_ENET PROFF_SCC2
439#define CPM_CR_ENET CPM_CR_CH_SCC2
440#define SCC_ENET 1
441#define PA_ENET_RXD ((ushort)0x0004)
442#define PA_ENET_TXD ((ushort)0x0008)
443#define PA_ENET_TCLK ((ushort)0x0100)
444#define PA_ENET_RCLK ((ushort)0x0200)
445#define PB_ENET_TENA ((uint)0x00002000)
446#define PC_ENET_CLSN ((ushort)0x0040)
447#define PC_ENET_RENA ((ushort)0x0080)
448
449/* BSE uses port B and C bits for PHY control also.
450*/
451#define PB_BSE_POWERUP ((uint)0x00000004)
452#define PB_BSE_FDXDIS ((uint)0x00008000)
453#define PC_BSE_LOOPBACK ((ushort)0x0800)
454
455#define SICR_ENET_MASK ((uint)0x0000ff00)
456#define SICR_ENET_CLKRT ((uint)0x00002c00)
457#endif /* CONFIG_BSEIP */
458
wdenk3bac3512003-03-12 10:41:04 +0000459/*** ELPT860 *********************************************************/
460
461#ifdef CONFIG_ELPT860
462/* Bits in parallel I/O port registers that have to be set/cleared
463 * to configure the pins for SCC1 use.
464 */
465# define PROFF_ENET PROFF_SCC1
466# define CPM_CR_ENET CPM_CR_CH_SCC1
467# define SCC_ENET 0
468
469# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
470# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
471# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
472# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
473
474# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
475# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
476# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
477
478/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
479 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
480 */
481# define SICR_ENET_MASK ((uint)0x000000FF)
482# define SICR_ENET_CLKRT ((uint)0x00000025)
483#endif /* CONFIG_ELPT860 */
484
wdenkfe8c2802002-11-03 00:38:21 +0000485/*** ESTEEM 192E **************************************************/
486#ifdef CONFIG_ESTEEM192E
487/* ESTEEM192E
488 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
489 * is very similar to the RPX-Lite configuration.
490 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
491 */
492
493#define PROFF_ENET PROFF_SCC2
494#define CPM_CR_ENET CPM_CR_CH_SCC2
495#define SCC_ENET 1
496
497#define PA_ENET_RXD ((ushort)0x0004)
498#define PA_ENET_TXD ((ushort)0x0008)
499#define PA_ENET_TCLK ((ushort)0x0200)
500#define PA_ENET_RCLK ((ushort)0x0800)
501#define PB_ENET_TENA ((uint)0x00002000)
502#define PC_ENET_CLSN ((ushort)0x0040)
503#define PC_ENET_RENA ((ushort)0x0080)
504
505#define SICR_ENET_MASK ((uint)0x0000ff00)
506#define SICR_ENET_CLKRT ((uint)0x00003d00)
507
508#define PB_ENET_LOOPBACK ((uint)0x00004000)
509#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
510
511#endif
512
wdenk384ae022002-11-05 00:17:55 +0000513/*** FPS850L, FPS860L ************************************************/
wdenkfe8c2802002-11-03 00:38:21 +0000514
wdenk384ae022002-11-05 00:17:55 +0000515#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
wdenkfe8c2802002-11-03 00:38:21 +0000516/* Bits in parallel I/O port registers that have to be set/cleared
wdenk384ae022002-11-05 00:17:55 +0000517 * to configure the pins for SCC2 use.
wdenkfe8c2802002-11-03 00:38:21 +0000518 */
519#define PROFF_ENET PROFF_SCC2
520#define CPM_CR_ENET CPM_CR_CH_SCC2
521#define SCC_ENET 1
522#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
523#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
524#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
525#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
526
527#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
528#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
529#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
530
531/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
532 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
533 */
534#define SICR_ENET_MASK ((uint)0x0000ff00)
535#define SICR_ENET_CLKRT ((uint)0x00002600)
wdenk384ae022002-11-05 00:17:55 +0000536#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
wdenkfe8c2802002-11-03 00:38:21 +0000537
wdenkfe8c2802002-11-03 00:38:21 +0000538/*** IP860 **********************************************************/
539
540#if defined(CONFIG_IP860)
541/* Bits in parallel I/O port registers that have to be set/cleared
542 * to configure the pins for SCC1 use.
543 */
544#define PROFF_ENET PROFF_SCC1
545#define CPM_CR_ENET CPM_CR_CH_SCC1
546#define SCC_ENET 0
547#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
548#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
549#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
550#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
551
552#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
553#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
554#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
555
556#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
557#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
558
559/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
560 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
561 */
562#define SICR_ENET_MASK ((uint)0x000000ff)
563#define SICR_ENET_CLKRT ((uint)0x0000002C)
564#endif /* CONFIG_IP860 */
565
566/*** IVMS8 **********************************************************/
567
568/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
569
570#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
571
572#define FEC_ENET /* use FEC for EThernet */
573#undef SCC_ENET
574
575#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
576
577#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
578
579#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
580#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
581#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
582#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
583#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
584#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
585#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
586#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
587#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
588#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
589#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
590#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
591#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
592
593#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
594
595#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
596
wdenk0608e042004-03-25 19:29:38 +0000597/*** KUP4K, KUP4X ****************************************************/
598/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
wdenk56f94be2002-11-05 16:35:14 +0000599
wdenk0608e042004-03-25 19:29:38 +0000600#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
wdenk56f94be2002-11-05 16:35:14 +0000601
602#define FEC_ENET /* use FEC for EThernet */
603#undef SCC_ENET
604
605#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
606
607#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
608
609#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
610#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
611#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
612#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
613#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
614#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
615#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
616#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
617#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
618#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
619#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
620#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
621#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
622
623#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
624
625#endif /* CONFIG_KUP4K */
626
wdenkfe8c2802002-11-03 00:38:21 +0000627/*** LWMON **********************************************************/
628
wdenk281e00a2004-08-01 22:48:16 +0000629#if defined(CONFIG_LWMON)
wdenkfe8c2802002-11-03 00:38:21 +0000630/* Bits in parallel I/O port registers that have to be set/cleared
631 * to configure the pins for SCC2 use.
632 */
633#define PROFF_ENET PROFF_SCC2
634#define CPM_CR_ENET CPM_CR_CH_SCC2
635#define SCC_ENET 1
636#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
637#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
638#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
639#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
640
641#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
642
643#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
644#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
645
646/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
647 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
648 */
649#define SICR_ENET_MASK ((uint)0x0000ff00)
650#define SICR_ENET_CLKRT ((uint)0x00003E00)
651#endif /* CONFIG_LWMON */
652
Heiko Schocherd0449542009-03-12 07:37:28 +0100653/*** KM8XX *********************************************************/
Heiko Schocher381e4e62008-01-11 01:12:06 +0100654
Heiko Schocherd0449542009-03-12 07:37:28 +0100655/* The KM8XX Service Module uses SCC3 for Ethernet */
Heiko Schocher381e4e62008-01-11 01:12:06 +0100656
Heiko Schocherd0449542009-03-12 07:37:28 +0100657#ifdef CONFIG_KM8XX
Heiko Schocher381e4e62008-01-11 01:12:06 +0100658#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
659#define CPM_CR_ENET CPM_CR_CH_SCC3
660#define SCC_ENET 2
661#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
662#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
663#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
664#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
665
666#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
667
668#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
669#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
670
671/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
672 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
673 */
674#define SICR_ENET_MASK ((uint)0x00FF0000)
675#define SICR_ENET_CLKRT ((uint)0x00250000)
Heiko Schocherd0449542009-03-12 07:37:28 +0100676#endif /* CONFIG_KM8XX */
Heiko Schocher381e4e62008-01-11 01:12:06 +0100677
wdenk608c9142003-01-13 23:54:46 +0000678/*** NETVIA *******************************************************/
679
680#if defined(CONFIG_NETVIA)
681/* Bits in parallel I/O port registers that have to be set/cleared
682 * to configure the pins for SCC2 use.
683 */
684#define PROFF_ENET PROFF_SCC2
685#define CPM_CR_ENET CPM_CR_CH_SCC2
686#define SCC_ENET 1
687#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
688#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
689#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
690#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
691
wdenk993cad92003-06-26 22:04:09 +0000692#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
693# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
694#elif CONFIG_NETVIA_VERSION >= 2
695# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
696#endif
697
wdenk608c9142003-01-13 23:54:46 +0000698#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
699
700#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
701#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
702
703/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
704 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
705 */
706#define SICR_ENET_MASK ((uint)0x0000ff00)
707#define SICR_ENET_CLKRT ((uint)0x00002f00)
708
709#endif /* CONFIG_NETVIA */
710
wdenkfe8c2802002-11-03 00:38:21 +0000711/*** SM850 *********************************************************/
712
713/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
714
715#ifdef CONFIG_SM850
716#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
717#define CPM_CR_ENET CPM_CR_CH_SCC3
718#define SCC_ENET 2
719#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
720#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
721#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
722#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
723
724#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
725#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
726
727#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
728#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
729
730/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
731 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
732 */
733#define SICR_ENET_MASK ((uint)0x00FF0000)
734#define SICR_ENET_CLKRT ((uint)0x00260000)
735#endif /* CONFIG_SM850 */
736
737/*** SPD823TS ******************************************************/
738
739#ifdef CONFIG_SPD823TS
740/* Bits in parallel I/O port registers that have to be set/cleared
741 * to configure the pins for SCC2 use.
742 */
743#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
744#define CPM_CR_ENET CPM_CR_CH_SCC2
745#define SCC_ENET 1
746#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
747#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
748#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
749#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
750#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
751#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
752
753#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
754
755#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
756#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
757#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
758
759/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
760 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
761 */
762#define SICR_ENET_MASK ((uint)0x0000ff00)
763#define SICR_ENET_CLKRT ((uint)0x00002E00)
764#endif /* CONFIG_SPD823TS */
765
Wolfgang Denk1b0757e2012-10-24 02:36:15 +0000766/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
wdenkfe8c2802002-11-03 00:38:21 +0000767
768#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
Masahiro Yamadac750b9c2014-06-20 13:54:53 +0900769 defined(CONFIG_R360MPI) || \
Wolfgang Denk1b0757e2012-10-24 02:36:15 +0000770 defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
771 defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
772 defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
773 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200774
wdenkfe8c2802002-11-03 00:38:21 +0000775/* Bits in parallel I/O port registers that have to be set/cleared
776 * to configure the pins for SCC2 use.
777 */
778#define PROFF_ENET PROFF_SCC2
779#define CPM_CR_ENET CPM_CR_CH_SCC2
Wolfgang Denk2b4f7782008-01-15 17:21:28 +0100780#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
wdenkfe8c2802002-11-03 00:38:21 +0000781#define SCC_ENET 1
Wolfgang Denk2b4f7782008-01-15 17:21:28 +0100782#endif
wdenkfe8c2802002-11-03 00:38:21 +0000783#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
784#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
785#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
786#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
787
788#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
789
790#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
791#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
792#if defined(CONFIG_R360MPI)
793#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
794#endif /* CONFIG_R360MPI */
795
796/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
797 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
798 */
799#define SICR_ENET_MASK ((uint)0x0000ff00)
800#define SICR_ENET_CLKRT ((uint)0x00002600)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200801
802# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
803#define FEC_ENET
804# endif /* CONFIG_FEC_ENET */
805
wdenk71f95112003-06-15 22:40:42 +0000806#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
wdenkfe8c2802002-11-03 00:38:21 +0000807
wdenkd4ca31c2004-01-02 14:00:00 +0000808/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
wdenkfe8c2802002-11-03 00:38:21 +0000809
wdenk71f95112003-06-15 22:40:42 +0000810#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
811 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
wdenkd4ca31c2004-01-02 14:00:00 +0000812 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
813 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
wdenkfe8c2802002-11-03 00:38:21 +0000814
815# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
816
817/* Bits in parallel I/O port registers that have to be set/cleared
818 * to configure the pins for SCC1 use.
819 */
820#define PROFF_ENET PROFF_SCC1
821#define CPM_CR_ENET CPM_CR_CH_SCC1
822#define SCC_ENET 0
823#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
824#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
825#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
826#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
827
828#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
829#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
830#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
831
832/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
833 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
834 */
835#define SICR_ENET_MASK ((uint)0x000000ff)
836#define SICR_ENET_CLKRT ((uint)0x00000026)
837
838# endif /* CONFIG_SCC1_ENET */
839
840# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
841
842#define FEC_ENET
843
844#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
845#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
846#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
847#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
848#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
849#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
850#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
851#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
852#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
853#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
854#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
855#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
856#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
857
858#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
859
860# endif /* CONFIG_FEC_ENET */
wdenk71f95112003-06-15 22:40:42 +0000861#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
wdenkfe8c2802002-11-03 00:38:21 +0000862
wdenkfe8c2802002-11-03 00:38:21 +0000863/*********************************************************************/
864
865/* SCC Event register as used by Ethernet.
866*/
867#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
868#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
869#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
870#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
871#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
872#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
873
874/* SCC Mode Register (PSMR) as used by Ethernet.
875*/
876#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
877#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
878#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
879#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
880#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
881#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
882#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
883#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
884#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
885#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
886#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
887#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
888#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
889
890/* Buffer descriptor control/status used by Ethernet receive.
891*/
892#define BD_ENET_RX_EMPTY ((ushort)0x8000)
893#define BD_ENET_RX_WRAP ((ushort)0x2000)
894#define BD_ENET_RX_INTR ((ushort)0x1000)
895#define BD_ENET_RX_LAST ((ushort)0x0800)
896#define BD_ENET_RX_FIRST ((ushort)0x0400)
897#define BD_ENET_RX_MISS ((ushort)0x0100)
898#define BD_ENET_RX_LG ((ushort)0x0020)
899#define BD_ENET_RX_NO ((ushort)0x0010)
900#define BD_ENET_RX_SH ((ushort)0x0008)
901#define BD_ENET_RX_CR ((ushort)0x0004)
902#define BD_ENET_RX_OV ((ushort)0x0002)
903#define BD_ENET_RX_CL ((ushort)0x0001)
904#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
905
906/* Buffer descriptor control/status used by Ethernet transmit.
907*/
908#define BD_ENET_TX_READY ((ushort)0x8000)
909#define BD_ENET_TX_PAD ((ushort)0x4000)
910#define BD_ENET_TX_WRAP ((ushort)0x2000)
911#define BD_ENET_TX_INTR ((ushort)0x1000)
912#define BD_ENET_TX_LAST ((ushort)0x0800)
913#define BD_ENET_TX_TC ((ushort)0x0400)
914#define BD_ENET_TX_DEF ((ushort)0x0200)
915#define BD_ENET_TX_HB ((ushort)0x0100)
916#define BD_ENET_TX_LC ((ushort)0x0080)
917#define BD_ENET_TX_RL ((ushort)0x0040)
918#define BD_ENET_TX_RCMASK ((ushort)0x003c)
919#define BD_ENET_TX_UN ((ushort)0x0002)
920#define BD_ENET_TX_CSL ((ushort)0x0001)
921#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
922
923/* SCC as UART
924*/
925typedef struct scc_uart {
926 sccp_t scc_genscc;
927 uint scc_res1; /* Reserved */
928 uint scc_res2; /* Reserved */
929 ushort scc_maxidl; /* Maximum idle chars */
930 ushort scc_idlc; /* temp idle counter */
931 ushort scc_brkcr; /* Break count register */
932 ushort scc_parec; /* receive parity error counter */
933 ushort scc_frmec; /* receive framing error counter */
934 ushort scc_nosec; /* receive noise counter */
935 ushort scc_brkec; /* receive break condition counter */
936 ushort scc_brkln; /* last received break length */
937 ushort scc_uaddr1; /* UART address character 1 */
938 ushort scc_uaddr2; /* UART address character 2 */
939 ushort scc_rtemp; /* Temp storage */
940 ushort scc_toseq; /* Transmit out of sequence char */
941 ushort scc_char1; /* control character 1 */
942 ushort scc_char2; /* control character 2 */
943 ushort scc_char3; /* control character 3 */
944 ushort scc_char4; /* control character 4 */
945 ushort scc_char5; /* control character 5 */
946 ushort scc_char6; /* control character 6 */
947 ushort scc_char7; /* control character 7 */
948 ushort scc_char8; /* control character 8 */
949 ushort scc_rccm; /* receive control character mask */
950 ushort scc_rccr; /* receive control character register */
951 ushort scc_rlbc; /* receive last break character */
952} scc_uart_t;
953
954/* SCC Event and Mask registers when it is used as a UART.
955*/
956#define UART_SCCM_GLR ((ushort)0x1000)
957#define UART_SCCM_GLT ((ushort)0x0800)
958#define UART_SCCM_AB ((ushort)0x0200)
959#define UART_SCCM_IDL ((ushort)0x0100)
960#define UART_SCCM_GRA ((ushort)0x0080)
961#define UART_SCCM_BRKE ((ushort)0x0040)
962#define UART_SCCM_BRKS ((ushort)0x0020)
963#define UART_SCCM_CCR ((ushort)0x0008)
964#define UART_SCCM_BSY ((ushort)0x0004)
965#define UART_SCCM_TX ((ushort)0x0002)
966#define UART_SCCM_RX ((ushort)0x0001)
967
968/* The SCC PSMR when used as a UART.
969*/
970#define SCU_PSMR_FLC ((ushort)0x8000)
971#define SCU_PSMR_SL ((ushort)0x4000)
972#define SCU_PSMR_CL ((ushort)0x3000)
973#define SCU_PSMR_UM ((ushort)0x0c00)
974#define SCU_PSMR_FRZ ((ushort)0x0200)
975#define SCU_PSMR_RZS ((ushort)0x0100)
976#define SCU_PSMR_SYN ((ushort)0x0080)
977#define SCU_PSMR_DRT ((ushort)0x0040)
978#define SCU_PSMR_PEN ((ushort)0x0010)
979#define SCU_PSMR_RPM ((ushort)0x000c)
980#define SCU_PSMR_REVP ((ushort)0x0008)
981#define SCU_PSMR_TPM ((ushort)0x0003)
982#define SCU_PSMR_TEVP ((ushort)0x0003)
983
984/* CPM Transparent mode SCC.
985 */
986typedef struct scc_trans {
987 sccp_t st_genscc;
988 uint st_cpres; /* Preset CRC */
989 uint st_cmask; /* Constant mask for CRC */
990} scc_trans_t;
991
992#define BD_SCC_TX_LAST ((ushort)0x0800)
993
994/* IIC parameter RAM.
995*/
996typedef struct iic {
997 ushort iic_rbase; /* Rx Buffer descriptor base address */
998 ushort iic_tbase; /* Tx Buffer descriptor base address */
999 u_char iic_rfcr; /* Rx function code */
1000 u_char iic_tfcr; /* Tx function code */
1001 ushort iic_mrblr; /* Max receive buffer length */
1002 uint iic_rstate; /* Internal */
1003 uint iic_rdp; /* Internal */
1004 ushort iic_rbptr; /* Internal */
1005 ushort iic_rbc; /* Internal */
1006 uint iic_rxtmp; /* Internal */
1007 uint iic_tstate; /* Internal */
1008 uint iic_tdp; /* Internal */
1009 ushort iic_tbptr; /* Internal */
1010 ushort iic_tbc; /* Internal */
1011 uint iic_txtmp; /* Internal */
1012 uint iic_res; /* reserved */
1013 ushort iic_rpbase; /* Relocation pointer */
1014 ushort iic_res2; /* reserved */
1015} iic_t;
1016
1017/* SPI parameter RAM.
1018*/
1019typedef struct spi {
1020 ushort spi_rbase; /* Rx Buffer descriptor base address */
1021 ushort spi_tbase; /* Tx Buffer descriptor base address */
1022 u_char spi_rfcr; /* Rx function code */
1023 u_char spi_tfcr; /* Tx function code */
1024 ushort spi_mrblr; /* Max receive buffer length */
1025 uint spi_rstate; /* Internal */
1026 uint spi_rdp; /* Internal */
1027 ushort spi_rbptr; /* Internal */
1028 ushort spi_rbc; /* Internal */
1029 uint spi_rxtmp; /* Internal */
1030 uint spi_tstate; /* Internal */
1031 uint spi_tdp; /* Internal */
1032 ushort spi_tbptr; /* Internal */
1033 ushort spi_tbc; /* Internal */
1034 uint spi_txtmp; /* Internal */
1035 uint spi_res;
1036 ushort spi_rpbase; /* Relocation pointer */
1037 ushort spi_res2;
1038} spi_t;
1039
1040/* SPI Mode register.
1041*/
1042#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1043#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1044#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1045#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1046#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1047#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1048#define SPMODE_EN ((ushort)0x0100) /* Enable */
1049#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1050#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1051
1052#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1053#define SPMODE_PM(x) ((x) &0xF)
1054
1055/* HDLC parameter RAM.
1056*/
1057
1058typedef struct hdlc_pram_s {
1059 /*
1060 * SCC parameter RAM
1061 */
1062 ushort rbase; /* Rx Buffer descriptor base address */
1063 ushort tbase; /* Tx Buffer descriptor base address */
1064 uchar rfcr; /* Rx function code */
1065 uchar tfcr; /* Tx function code */
1066 ushort mrblr; /* Rx buffer length */
1067 ulong rstate; /* Rx internal state */
1068 ulong rptr; /* Rx internal data pointer */
1069 ushort rbptr; /* rb BD Pointer */
1070 ushort rcount; /* Rx internal byte count */
1071 ulong rtemp; /* Rx temp */
1072 ulong tstate; /* Tx internal state */
1073 ulong tptr; /* Tx internal data pointer */
1074 ushort tbptr; /* Tx BD pointer */
1075 ushort tcount; /* Tx byte count */
1076 ulong ttemp; /* Tx temp */
1077 ulong rcrc; /* temp receive CRC */
1078 ulong tcrc; /* temp transmit CRC */
1079 /*
1080 * HDLC specific parameter RAM
1081 */
1082 uchar res[4]; /* reserved */
1083 ulong c_mask; /* CRC constant */
1084 ulong c_pres; /* CRC preset */
1085 ushort disfc; /* discarded frame counter */
1086 ushort crcec; /* CRC error counter */
1087 ushort abtsc; /* abort sequence counter */
1088 ushort nmarc; /* nonmatching address rx cnt */
1089 ushort retrc; /* frame retransmission cnt */
1090 ushort mflr; /* maximum frame length reg */
1091 ushort max_cnt; /* maximum length counter */
1092 ushort rfthr; /* received frames threshold */
1093 ushort rfcnt; /* received frames count */
1094 ushort hmask; /* user defined frm addr mask */
1095 ushort haddr1; /* user defined frm address 1 */
1096 ushort haddr2; /* user defined frm address 2 */
1097 ushort haddr3; /* user defined frm address 3 */
1098 ushort haddr4; /* user defined frm address 4 */
1099 ushort tmp; /* temp */
1100 ushort tmp_mb; /* temp */
1101} hdlc_pram_t;
1102
1103/* CPM interrupts. There are nearly 32 interrupts generated by CPM
1104 * channels or devices. All of these are presented to the PPC core
1105 * as a single interrupt. The CPM interrupt handler dispatches its
1106 * own handlers, in a similar fashion to the PPC core handler. We
1107 * use the table as defined in the manuals (i.e. no special high
1108 * priority and SCC1 == SCCa, etc...).
1109 */
1110#define CPMVEC_NR 32
wdenk7c7a23b2002-12-07 00:20:59 +00001111#define CPMVEC_OFFSET 0x00010000
1112#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1113#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1114#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1115#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1116#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1117#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1118#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1119#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1120#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1121#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1122#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1123#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1124#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1125#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1126#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1127#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1128#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1129#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1130#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1131#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1132#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1133#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1134#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1135#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1136#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1137#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1138#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1139#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1140#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
wdenkfe8c2802002-11-03 00:38:21 +00001141
1142extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1143
1144/* CPM interrupt configuration vector.
1145*/
1146#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1147#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1148#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1149#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1150#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1151#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1152#define CICR_IEN ((uint)0x00000080) /* Int. enable */
1153#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1154#endif /* __CPM_8XX__ */