blob: cb6f86272111cbb16042e20011be8a7e4cb0594f [file] [log] [blame]
Masahiro Yamada3365b4e2015-07-21 14:04:22 +09001/*
2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Masahiro Yamada3365b4e2015-07-21 14:04:22 +09007#include <linux/io.h>
8#include <mach/bcu-regs.h>
Masahiro Yamada323d1f92015-09-22 00:27:39 +09009#include <mach/init.h>
Masahiro Yamada3365b4e2015-07-21 14:04:22 +090010
11#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
12
Masahiro Yamada323d1f92015-09-22 00:27:39 +090013int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
Masahiro Yamada3365b4e2015-07-21 14:04:22 +090014{
15 int shift;
16
17 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
18 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
19 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
20 /*
21 * 0xe0000000-0xefffffff: Ex-bus
22 * 0xf0000000-0xfbffffff: ASM bus
23 * 0xfc000000-0xffffffff: OCM bus
24 */
25 writel(0x24440000, BCSCR5);
26
27 /* Specify DDR channel */
Masahiro Yamada323d1f92015-09-22 00:27:39 +090028 shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
Masahiro Yamada3365b4e2015-07-21 14:04:22 +090029 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
30
31 shift -= 32;
32 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
33
34 shift -= 32;
35 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
Masahiro Yamada323d1f92015-09-22 00:27:39 +090036
37 return 0;
Masahiro Yamada3365b4e2015-07-21 14:04:22 +090038}