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wdenke69b4b82002-09-17 21:26:59 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke69b4b82002-09-17 21:26:59 +00006 */
7
8/* common srom defs */
9#define FIRST_DEVICE 0x00
10#define SECOND_DEVICE 0x04
11#define FIRST_BLOCK 0x00
12#define SECOND_BLOCK 0x02
13#define BLOCK_SIZE 0x100
14#define ERROR (-1)
15
16#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100
17#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100
18
19#define CPU_TYPE_740 0x08
20#define CPU_TYPE_750 0x08
21#define CPU_TYPE ((get_pvr()>>16)&0xffff)
22
23#define ABS(x) ((x<0)?-x:x)
24#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
25
26/* bab7xx ELTEC srom */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220)
28#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221)
wdenke69b4b82002-09-17 21:26:59 +000029
30/* srom at mpc107 */
31#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */
32#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */
33#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */
34#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */
35#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */
36#define MPC107_I2C_TIMEOUT 10000000
37
38/* i82559 */
39#define EE_ADDR_BITS 6
40#define EE_SIZE 0x40 /* 0x40 words */
41#define EE_CHECKSUM 0xBABA
42
43/* dc21143 */
44#define DEC_SROM_SIZE 128
45
46
47/*
48 * structure of revision srom
49 */
50typedef struct {
51 char magic[8]; /* 000 - Magic number */
52 char revrev[2]; /* 008 - Revision of structure */
53 unsigned short size; /* 00A - Size of CRC area */
54 unsigned long crc; /* 00C - CRC */
55 char board[16]; /* 010 - Board Revision information */
56 char option[4][16]; /* 020 - Option Revision information */
57 char serial[8]; /* 060 - Board serial number */
58 char etheraddr[6]; /* 068 - Ethernet node addresse */
59 char reserved[2]; /* 06E - Reserved */
60 char revision[7][2]; /* 070 - Revision codes */
61 char category[2]; /* 07E - Category codes */
62 char text[64]; /* 080 - Text field */
63 char res[64]; /* 0C0 - Reserved */
64} revinfo;
65
66unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
67int el_srom_load (unsigned char addr, unsigned char *buf, int cnt,
wdenk8bde7f72003-06-27 21:31:46 +000068 unsigned char device, unsigned char block);
wdenke69b4b82002-09-17 21:26:59 +000069int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
wdenk8bde7f72003-06-27 21:31:46 +000070 unsigned char device, unsigned char block);
wdenke69b4b82002-09-17 21:26:59 +000071
72int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
73int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
74int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
wdenk8bde7f72003-06-27 21:31:46 +000075 unsigned char offset, unsigned char val);
wdenke69b4b82002-09-17 21:26:59 +000076int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
wdenk8bde7f72003-06-27 21:31:46 +000077 unsigned char device, unsigned char block);
wdenke69b4b82002-09-17 21:26:59 +000078int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
wdenk8bde7f72003-06-27 21:31:46 +000079 unsigned char device, unsigned char block);
wdenke69b4b82002-09-17 21:26:59 +000080
81int dc_srom_load (unsigned short *dest);
82int dc_srom_store (unsigned short *src);
83
84unsigned short eepro100_srom_checksum (unsigned short *sromdata);
85void eepro100_srom_load (unsigned short *destination);
86int eepro100_srom_store (unsigned short *source);