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Wolfgang Denk8f79e4c2005-08-10 15:14:32 +02001/*
Wolfgang Denk5078cce2006-07-21 11:16:34 +02002 * (C) Copyright 2003-2006
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
41#define CONFIG_AEVFIFO 1
42#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
43
Becky Bruce31d82672008-05-08 19:02:12 -050044#define CONFIG_HIGH_BATS 1 /* High BATs supported */
45
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020046#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
47#define BOOTFLAG_WARM 0x02 /* Software reboot */
48
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020049/*
50 * Serial console configuration
51 */
52#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
54#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
55
56/*
57 * PCI Mapping:
58 * 0x40000000 - 0x4fffffff - PCI Memory
59 * 0x50000000 - 0x50ffffff - PCI IO Space
60 */
61#ifdef CONFIG_AEVFIFO
62#define CONFIG_PCI 1
63#define CONFIG_PCI_PNP 1
64/* #define CONFIG_PCI_SCAN_SHOW 1 */
TsiChung Liewf33fca22008-03-30 01:19:06 -050065#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020066
67#define CONFIG_PCI_MEM_BUS 0x40000000
68#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
69#define CONFIG_PCI_MEM_SIZE 0x10000000
70
71#define CONFIG_PCI_IO_BUS 0x50000000
72#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
73#define CONFIG_PCI_IO_SIZE 0x01000000
74
75#define CONFIG_NET_MULTI 1
76#define CONFIG_EEPRO100 1
77#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
78#define CONFIG_NS8382X 1
79#endif /* CONFIG_AEVFIFO */
80
81/* Partitions */
82#define CONFIG_MAC_PARTITION
83#define CONFIG_DOS_PARTITION
84#define CONFIG_ISO_PARTITION
85
86/* POST support */
87#define CONFIG_POST (CFG_POST_MEMORY | \
88 CFG_POST_CPU | \
89 CFG_POST_I2C)
90
91#ifdef CONFIG_POST
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020092/* preserve space for the post_word at end of on-chip SRAM */
93#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020094#endif
95
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020096
Jon Loeliger0b361c92007-07-04 22:31:42 -050097/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050098 * BOOTP options
99 */
100#define CONFIG_BOOTP_BOOTFILESIZE
101#define CONFIG_BOOTP_BOOTPATH
102#define CONFIG_BOOTP_GATEWAY
103#define CONFIG_BOOTP_HOSTNAME
104
105
106/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500107 * Command line configuration.
108 */
109#include <config_cmd_default.h>
110
111#define CONFIG_CMD_ASKENV
112#define CONFIG_CMD_DATE
113#define CONFIG_CMD_DHCP
114#define CONFIG_CMD_ECHO
115#define CONFIG_CMD_EEPROM
116#define CONFIG_CMD_I2C
117#define CONFIG_CMD_MII
118#define CONFIG_CMD_NFS
119#define CONFIG_CMD_PCI
120#define CONFIG_CMD_PING
Jon Loeliger0b361c92007-07-04 22:31:42 -0500121#define CONFIG_CMD_REGINFO
122#define CONFIG_CMD_SNTP
123
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500124#ifdef CONFIG_POST
125#define CONFIG_CMD_DIAG
126#endif
127
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200128
129#define CONFIG_TIMESTAMP /* display image timestamps */
130
131#if (TEXT_BASE == 0xFC000000) /* Boot low */
132# define CFG_LOWBOOT 1
133#endif
134
135/*
136 * Autobooting
137 */
138#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
139
140#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100141 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200142 "echo"
143
144#undef CONFIG_BOOTARGS
145
146#define CONFIG_EXTRA_ENV_SETTINGS \
147 "netdev=eth0\0" \
148 "rootpath=/opt/eldk/ppc_6xx\0" \
149 "ramargs=setenv bootargs root=/dev/ram rw\0" \
150 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100151 "nfsroot=${serverip}:${rootpath} " \
152 "console=ttyS0,${baudrate}\0" \
153 "addip=setenv bootargs ${bootargs} " \
154 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
155 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200156 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100157 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200158 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100159 "bootm ${kernel_addr}\0" \
160 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200161 "bootfile=/tftpboot/tqm5200/uImage\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100162 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200163 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
164 "update=protect off FC000000 FC05FFFF;" \
165 "erase FC000000 FC05FFFF;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100166 "cp.b 200000 FC000000 ${filesize};" \
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200167 "protect on FC000000 FC05FFFF\0" \
168 ""
169
170#define CONFIG_BOOTCOMMAND "run net_nfs"
171
172/*
173 * IPB Bus clocking configuration.
174 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200175#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200176
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200177#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200178/*
179 * PCI Bus clocking configuration
180 *
181 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Wolfgang Denk725671c2007-06-06 16:26:56 +0200182 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200183 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200184 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200185#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200186#endif
187
188/*
189 * I2C configuration
190 */
191#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
192#ifdef CONFIG_TQM5200_REV100
193#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
194#else
195#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
196#endif
197
198/*
199 * I2C clock frequency
200 *
201 * Please notice, that the resulting clock frequency could differ from the
202 * configured value. This is because the I2C clock is derived from system
203 * clock over a frequency divider with only a few divider values. U-boot
204 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
205 * approximation allways lies below the configured value, never above.
206 */
207#define CFG_I2C_SPEED 100000 /* 100 kHz */
208#define CFG_I2C_SLAVE 0x7F
209
210/*
211 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
212 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
213 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
214 * same configuration could be used.
215 */
216#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
217#define CFG_I2C_EEPROM_ADDR_LEN 2
218#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
219#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
220
221/*
222 * Flash configuration
223 */
224#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
225
226/* use CFI flash driver if no module variant is spezified */
227#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
228#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
229#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
230#define CFG_FLASH_EMPTY_INFO
231#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
232#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
233#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
234
235#if !defined(CFG_LOWBOOT)
236#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
237#else /* CFG_LOWBOOT */
238#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
239#endif /* CFG_LOWBOOT */
240#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
241 (= chip selects) */
242#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
243#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
244
245
246/*
247 * Environment settings
248 */
249#define CFG_ENV_IS_IN_FLASH 1
250#define CFG_ENV_SIZE 0x10000
251#define CFG_ENV_SECT_SIZE 0x20000
252#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
253#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
254
255/*
256 * Memory map
257 */
258#define CFG_MBAR 0xF0000000
259#define CFG_SDRAM_BASE 0x00000000
260#define CFG_DEFAULT_MBAR 0x80000000
261
262/* Use ON-Chip SRAM until RAM will be available */
263#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
264#ifdef CONFIG_POST
265/* preserve space for the post_word at end of on-chip SRAM */
266#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
267#else
268#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
269#endif
270
271
272#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
273#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
274#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
275
276#define CFG_MONITOR_BASE TEXT_BASE
277#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
278# define CFG_RAMBOOT 1
279#endif
280
281#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
282#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
283#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
284
285/*
286 * Ethernet configuration
287 */
288#define CONFIG_MPC5xxx_FEC 1
289/*
290 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
291 */
292/* #define CONFIG_FEC_10MBIT 1 */
293#define CONFIG_PHY_ADDR 0x00
294
295/*
296 * GPIO configuration
297 *
298 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
299 * Bit 0 (mask: 0x80000000): 1
300 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
301 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
302 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
303 * Use for REV200 STK52XX boards. Do not use with REV100 modules
304 * (because, there I2C1 is used as I2C bus)
305 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
306 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
307 * 000 -> All PSC2 pins are GIOPs
308 * 001 -> CAN1/2 on PSC2 pins
309 * Use for REV100 STK52xx boards
310 * use PSC6:
311 * on STK52xx:
312 * use as UART. Pins PSC6_0 to PSC6_3 are used.
313 * Bits 9:11 (mask: 0x00700000):
314 * 101 -> PSC6 : Extended POST test is not available
315 * on MINI-FAP and TQM5200_IB:
316 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
317 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
318 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
319 * tests.
320 */
321#define CFG_GPS_PORT_CONFIG 0x81500014
322
323/*
324 * RTC configuration
325 */
326#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
327
328/*
329 * Miscellaneous configurable options
330 */
331#define CFG_LONGHELP /* undef to save memory */
332#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500333#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200334#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
335#else
336#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
337#endif
338#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
339#define CFG_MAXARGS 16 /* max number of command args */
340#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
341
342/* Enable an alternate, more extensive memory test */
343#define CFG_ALT_MEMTEST
344
345#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
346#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
347
348#define CFG_LOAD_ADDR 0x100000 /* default load address */
349
350#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
351
Jon Loeliger0b361c92007-07-04 22:31:42 -0500352#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
353#if defined(CONFIG_CMD_KGDB)
354# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
355#endif
356
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200357/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500358 * Enable loopw command.
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200359 */
360#define CONFIG_LOOPW
361
362/*
363 * Various low-level settings
364 */
365#if defined(CONFIG_MPC5200)
366#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
367#define CFG_HID0_FINAL HID0_ICE
368#else
369#define CFG_HID0_INIT 0
370#define CFG_HID0_FINAL 0
371#endif
372
373#define CFG_BOOTCS_START CFG_FLASH_BASE
374#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200375#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200376#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
377#else
378#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
379#endif
380#define CFG_CS0_START CFG_FLASH_BASE
381#define CFG_CS0_SIZE CFG_FLASH_SIZE
382
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200383#define CONFIG_LAST_STAGE_INIT
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200384
385/*
386 * SRAM - Do not map below 2 GB in address space, because this area is used
387 * for SDRAM autosizing.
388 */
389#define CFG_CS2_START 0xE5000000
390#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
391#define CFG_CS2_CFG 0x0004D930
392
393/*
394 * Grafic controller - Do not map below 2 GB in address space, because this
395 * area is used for SDRAM autosizing.
396 */
397#define SM501_FB_BASE 0xE0000000
398#define CFG_CS1_START (SM501_FB_BASE)
399#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
400#define CFG_CS1_CFG 0x8F48FF70
401#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
402
403#define CFG_CS_BURST 0x00000000
404#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
405
406#define CFG_RESET_ADDRESS 0xff000000
407
408#endif /* __CONFIG_H */