blob: bcab76d0509bc8bb1d7d53085e579e1cc9b74591 [file] [log] [blame]
Neil Armstrong59beb232018-04-23 16:19:23 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
4 * Copyright (C) 2018 BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
8 */
9
10#include <common.h>
11#include <adc.h>
12#include <clk.h>
13#include <dm.h>
14#include <regmap.h>
15#include <errno.h>
16#include <asm/io.h>
17#include <linux/math64.h>
18#include <linux/bitfield.h>
19
20#define MESON_SAR_ADC_REG0 0x00
21 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
22 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
23 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
24 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
25 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
26 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
27 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
28 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
29 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
30 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
31 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
32 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
33 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
34 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
35 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
36 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
37 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
38 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
39 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
40 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
41
42#define MESON_SAR_ADC_CHAN_LIST 0x04
43 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
44 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
45 (GENMASK(2, 0) << ((_chan) * 3))
46
47#define MESON_SAR_ADC_AVG_CNTL 0x08
48 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
49 (16 + ((_chan) * 2))
50 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
51 (GENMASK(17, 16) << ((_chan) * 2))
52 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
53 (0 + ((_chan) * 2))
54 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
55 (GENMASK(1, 0) << ((_chan) * 2))
56
57#define MESON_SAR_ADC_REG3 0x0c
58 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
59 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
60 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
61 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
62 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
63 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
64 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
65 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
66 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
67 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
68 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
69 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
70 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
71 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
72
73#define MESON_SAR_ADC_DELAY 0x10
74 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
75 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
76 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
77 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
78 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
79 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
80
81#define MESON_SAR_ADC_LAST_RD 0x14
82 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
83 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
84
85#define MESON_SAR_ADC_FIFO_RD 0x18
86 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
87 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
88
89#define MESON_SAR_ADC_AUX_SW 0x1c
90 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
91 (8 + (((_chan) - 2) * 3))
92 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
93 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
94 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
95 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
96 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
97 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
98 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
99
100#define MESON_SAR_ADC_CHAN_10_SW 0x20
101 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
102 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
103 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
104 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
105 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
117
118#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
119 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
120 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
121 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
122 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
123 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
136
137#define MESON_SAR_ADC_DELTA_10 0x28
138 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
139 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
140 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
141 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
142 #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
143 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
144 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
145 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
146
147/*
148 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
149 * and u-boot source served as reference). These only seem to be relevant on
150 * GXBB and newer.
151 */
152#define MESON_SAR_ADC_REG11 0x2c
153 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
154
155#define MESON_SAR_ADC_REG13 0x34
156 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
157
158#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
159#define MESON_SAR_ADC_TIMEOUT 100 /* ms */
160
161#define NUM_CHANNELS 8
162
163#define MILLION 1000000
164
165struct meson_saradc_data {
166 int num_bits;
167};
168
169struct meson_saradc_priv {
170 const struct meson_saradc_data *data;
171 struct regmap *regmap;
172 struct clk core_clk;
173 struct clk adc_clk;
174 bool initialized;
175 int active_channel;
176 int calibbias;
177 int calibscale;
178};
179
180static unsigned int
181meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
182{
183 u32 regval;
184
185 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
186
187 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
188}
189
190static int meson_saradc_lock(struct meson_saradc_priv *priv)
191{
192 uint val, timeout = 10000;
193
194 /* prevent BL30 from using the SAR ADC while we are using it */
195 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
196 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
197 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
198
199 /*
200 * wait until BL30 releases it's lock (so we can use the SAR ADC)
201 */
202 do {
203 udelay(1);
204 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
205 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
206
207 if (timeout < 0) {
208 printf("Timeout while waiting for BL30 unlock\n");
209 return -ETIMEDOUT;
210 }
211
212 return 0;
213}
214
215static void meson_saradc_unlock(struct meson_saradc_priv *priv)
216{
217 /* allow BL30 to use the SAR ADC again */
218 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
219 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
220}
221
222static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
223{
224 unsigned int count, tmp;
225
226 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
227 if (!meson_saradc_get_fifo_count(priv))
228 break;
229
230 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
231 }
232}
233
234static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
235{
236 int tmp;
237
238 /* use val_calib = scale * val_raw + offset calibration function */
239 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
240
241 return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
242}
243
244static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
245{
246 uint regval, timeout = 10000;
247
248 /*
249 * NOTE: we need a small delay before reading the status, otherwise
250 * the sample engine may not have started internally (which would
251 * seem to us that sampling is already finished).
252 */
253 do {
254 udelay(1);
255 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
256 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
257
258 if (timeout < 0)
259 return -ETIMEDOUT;
260
261 return 0;
262}
263
264static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
265 unsigned int channel, uint *val)
266{
267 uint regval, fifo_chan, fifo_val, count;
268 int ret;
269
270 ret = meson_saradc_wait_busy_clear(priv);
271 if (ret)
272 return ret;
273
274 count = meson_saradc_get_fifo_count(priv);
275 if (count != 1) {
276 printf("ADC FIFO has %d element(s) instead of one\n", count);
277 return -EINVAL;
278 }
279
280 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
281 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
282 if (fifo_chan != channel) {
283 printf("ADC FIFO entry belongs to channel %d instead of %d\n",
284 fifo_chan, channel);
285 return -EINVAL;
286 }
287
288 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
289 fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
290 *val = meson_saradc_calib_val(priv, fifo_val);
291
292 return 0;
293}
294
295static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
296{
297 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
298 MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
299 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
300
301 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
302 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
303 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
304
305 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
306 MESON_SAR_ADC_REG0_SAMPLING_START,
307 MESON_SAR_ADC_REG0_SAMPLING_START);
308}
309
310static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
311{
312 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
313 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
314
315 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
316 MESON_SAR_ADC_REG0_SAMPLING_STOP,
317 MESON_SAR_ADC_REG0_SAMPLING_STOP);
318
319 /* wait until all modules are stopped */
320 meson_saradc_wait_busy_clear(priv);
321
322 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
323 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
324}
325
326enum meson_saradc_avg_mode {
327 NO_AVERAGING = 0x0,
328 MEAN_AVERAGING = 0x1,
329 MEDIAN_AVERAGING = 0x2,
330};
331
332enum meson_saradc_num_samples {
333 ONE_SAMPLE = 0x0,
334 TWO_SAMPLES = 0x1,
335 FOUR_SAMPLES = 0x2,
336 EIGHT_SAMPLES = 0x3,
337};
338
339static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
340 unsigned int channel,
341 enum meson_saradc_avg_mode mode,
342 enum meson_saradc_num_samples samples)
343{
344 int val;
345
346 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
347 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
348 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
349 val);
350
351 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
352 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
353 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
354}
355
356static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
357 unsigned int channel)
358{
359 uint regval;
360
361 /*
362 * the SAR ADC engine allows sampling multiple channels at the same
363 * time. to keep it simple we're only working with one *internal*
364 * channel, which starts counting at index 0 (which means: count = 1).
365 */
366 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
367 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
368 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
369
370 /* map channel index 0 to the channel which we want to read */
371 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
372 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
373 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
374
375 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
376 channel);
377 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
378 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
379 regval);
380
381 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
382 channel);
383 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
384 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
385 regval);
386
387 if (channel == 6)
388 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
389 MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
390}
391
392static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
393 int chan, uint *val)
394{
395 int ret;
396
397 ret = meson_saradc_lock(priv);
398 if (ret)
399 return ret;
400
401 /* clear the FIFO to make sure we're not reading old values */
402 meson_saradc_clear_fifo(priv);
403
404 meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
405
406 meson_saradc_enable_channel(priv, chan);
407
408 meson_saradc_start_sample_engine(priv);
409 ret = meson_saradc_read_raw_sample(priv, chan, val);
410 meson_saradc_stop_sample_engine(priv);
411
412 meson_saradc_unlock(priv);
413
414 if (ret) {
415 printf("failed to read sample for channel %d: %d\n",
416 chan, ret);
417 return ret;
418 }
419
420 return 0;
421}
422
423static int meson_saradc_channel_data(struct udevice *dev, int channel,
424 unsigned int *data)
425{
426 struct meson_saradc_priv *priv = dev_get_priv(dev);
427
428 if (channel != priv->active_channel) {
429 pr_err("Requested channel is not active!");
430 return -EINVAL;
431 }
432
433 return meson_saradc_get_sample(priv, channel, data);
434}
435
436enum meson_saradc_chan7_mux_sel {
437 CHAN7_MUX_VSS = 0x0,
438 CHAN7_MUX_VDD_DIV4 = 0x1,
439 CHAN7_MUX_VDD_DIV2 = 0x2,
440 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
441 CHAN7_MUX_VDD = 0x4,
442 CHAN7_MUX_CH7_INPUT = 0x7,
443};
444
445static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
446 enum meson_saradc_chan7_mux_sel sel)
447{
448 u32 regval;
449
450 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
451 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
452 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
453
454 udelay(20);
455}
456
457static int meson_saradc_calib(struct meson_saradc_priv *priv)
458{
459 uint nominal0, nominal1, value0, value1;
460 int ret;
461
462 /* use points 25% and 75% for calibration */
463 nominal0 = (1 << priv->data->num_bits) / 4;
464 nominal1 = (1 << priv->data->num_bits) * 3 / 4;
465
466 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
467 udelay(20);
468 ret = meson_saradc_get_sample(priv, 7, &value0);
469 if (ret < 0)
470 goto out;
471
472 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
473 udelay(20);
474 ret = meson_saradc_get_sample(priv, 7, &value1);
475 if (ret < 0)
476 goto out;
477
478 if (value1 <= value0) {
479 ret = -EINVAL;
480 goto out;
481 }
482
483 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
484 value1 - value0);
485 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
486 MILLION);
487 ret = 0;
488out:
489 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
490
491 return ret;
492}
493
494static int meson_saradc_init(struct meson_saradc_priv *priv)
495{
496 uint regval;
497 int ret, i;
498
499 priv->calibscale = MILLION;
500
501 /*
502 * make sure we start at CH7 input since the other muxes are only used
503 * for internal calibration.
504 */
505 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
506
507 /*
508 * leave sampling delay and the input clocks as configured by
509 * BL30 to make sure BL30 gets the values it expects when
510 * reading the temperature sensor.
511 */
512 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
513 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
514 return 0;
515
516 meson_saradc_stop_sample_engine(priv);
517
518 /* update the channel 6 MUX to select the temperature sensor */
519 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
520 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
521 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
522
523 /* disable all channels by default */
524 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
525
526 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
527 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
528 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
529 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
530 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
531
532 /* delay between two samples = (10+1) * 1uS */
533 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
534 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
535 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
536 10));
537 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
538 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
539 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
540 0));
541
542 /* delay between two samples = (10+1) * 1uS */
543 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
544 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
545 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
546 10));
547 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
548 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
549 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
550 1));
551
552 /*
553 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
554 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
555 */
556 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
557 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
558 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
559 regval);
560 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
561 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
562 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
563 regval);
564
565 /*
566 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
567 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
568 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
569 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
570 */
571 regval = 0;
572 for (i = 2; i <= 7; i++)
573 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
574 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
575 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
576 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
577
578 ret = meson_saradc_lock(priv);
579 if (ret)
580 return ret;
581
582#if CONFIG_IS_ENABLED(CLK)
583 ret = clk_enable(&priv->core_clk);
584 if (ret)
585 return ret;
586#endif
587
588 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
589 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
590 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
591
592 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
593 MESON_SAR_ADC_REG11_BANDGAP_EN,
594 MESON_SAR_ADC_REG11_BANDGAP_EN);
595
596 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
597 MESON_SAR_ADC_REG3_ADC_EN,
598 MESON_SAR_ADC_REG3_ADC_EN);
599
600 udelay(5);
601
602#if CONFIG_IS_ENABLED(CLK)
603 ret = clk_enable(&priv->adc_clk);
604 if (ret)
605 return ret;
606#endif
607
608 meson_saradc_unlock(priv);
609
610 ret = meson_saradc_calib(priv);
611 if (ret) {
612 printf("calibration failed\n");
613 return -EIO;
614 }
615
616 return 0;
617}
618
619static int meson_saradc_start_channel(struct udevice *dev, int channel)
620{
621 struct meson_saradc_priv *priv = dev_get_priv(dev);
622
623 if (channel < 0 || channel >= NUM_CHANNELS) {
624 printf("Requested channel is invalid!");
625 return -EINVAL;
626 }
627
628 if (!priv->initialized) {
629 int ret;
630
631 ret = meson_saradc_init(priv);
632 if (ret)
633 return ret;
634
635 priv->initialized = true;
636 }
637
638 priv->active_channel = channel;
639
640 return 0;
641}
642
643static int meson_saradc_stop(struct udevice *dev)
644{
645 struct meson_saradc_priv *priv = dev_get_priv(dev);
646
647 priv->active_channel = -1;
648
649 return 0;
650}
651
652static int meson_saradc_probe(struct udevice *dev)
653{
654 struct meson_saradc_priv *priv = dev_get_priv(dev);
655 int ret;
656
657 ret = regmap_init_mem(dev, &priv->regmap);
658 if (ret)
659 return ret;
660
661#if CONFIG_IS_ENABLED(CLK)
662 ret = clk_get_by_name(dev, "core", &priv->core_clk);
663 if (ret)
664 return ret;
665
666 ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
667 if (ret)
668 return ret;
669#endif
670
671 priv->active_channel = -1;
672
673 return 0;
674}
675
676int meson_saradc_ofdata_to_platdata(struct udevice *dev)
677{
678 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
679 struct meson_saradc_priv *priv = dev_get_priv(dev);
680
681 priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
682
683 uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
684 uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
685 uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
686 uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
687
688 return 0;
689}
690
691static const struct adc_ops meson_saradc_ops = {
692 .start_channel = meson_saradc_start_channel,
693 .channel_data = meson_saradc_channel_data,
694 .stop = meson_saradc_stop,
695};
696
697static const struct meson_saradc_data gxbb_saradc_data = {
698 .num_bits = 10,
699};
700
701static const struct meson_saradc_data gxl_saradc_data = {
702 .num_bits = 12,
703};
704
705static const struct udevice_id meson_saradc_ids[] = {
706 { .compatible = "amlogic,meson-gxbb-saradc",
707 .data = (ulong)&gxbb_saradc_data },
708 { .compatible = "amlogic,meson-gxl-saradc",
709 .data = (ulong)&gxl_saradc_data },
710 { .compatible = "amlogic,meson-gxm-saradc",
711 .data = (ulong)&gxl_saradc_data },
712 { }
713};
714
715U_BOOT_DRIVER(meson_saradc) = {
716 .name = "meson_saradc",
717 .id = UCLASS_ADC,
718 .of_match = meson_saradc_ids,
719 .ops = &meson_saradc_ops,
720 .probe = meson_saradc_probe,
721 .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
722 .priv_auto_alloc_size = sizeof(struct meson_saradc_priv),
723};