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Tom Rix376aee72009-05-15 23:48:36 +02001/*
2 * (C) Copyright 2006-2009
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 * Tom Rix <Tom.Rix@windriver.com>
8 *
9 * Configuration settings for the TI OMAP3430 Zoom II board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
Tom Rix376aee72009-05-15 23:48:36 +020032
33/*
34 * High Level Configuration Options
35 */
36#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
37#define CONFIG_OMAP 1 /* in a TI OMAP core */
38#define CONFIG_OMAP34XX 1 /* which is a 34XX */
39#define CONFIG_OMAP3430 1 /* which is in a 3430 */
40#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
41
42#include <asm/arch/cpu.h> /* get chip and board defs */
43#include <asm/arch/omap3.h>
44
Dirk Behme3962c4f2009-05-31 12:44:41 +020045/*
46 * Display CPU and Board information
47 */
48#define CONFIG_DISPLAY_CPUINFO 1
49#define CONFIG_DISPLAY_BOARDINFO 1
50
Tom Rix376aee72009-05-15 23:48:36 +020051/* Clock Defines */
52#define V_OSCK 26000000 /* Clock output from T2 */
53#define V_SCLK (V_OSCK >> 1)
54
55#undef CONFIG_USE_IRQ /* no support for IRQs */
56#define CONFIG_MISC_INIT_R
57
58#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61#define CONFIG_REVISION_TAG 1
62
63/*
64 * Size of malloc() pool
65 */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040066#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Tom Rix376aee72009-05-15 23:48:36 +020067 /* Sector */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040068#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Tom Rix376aee72009-05-15 23:48:36 +020069#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
70 /* initial data */
71/*
72 * Hardware drivers
73 */
74
75/*
76 * NS16550 Configuration
Tom Rix660888b2009-05-31 12:44:37 +020077 * Zoom2 uses the TL16CP754C on the debug board
Tom Rix376aee72009-05-15 23:48:36 +020078 */
Tom Rix660888b2009-05-31 12:44:37 +020079#define CONFIG_SERIAL_MULTI 1
80/*
81 * 0 - 1 : first USB with respect to the left edge of the debug board
82 * 2 - 3 : second USB with respect to the left edge of the debug board
83 */
84#define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
85
86#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
Tom Rix376aee72009-05-15 23:48:36 +020087
88#define CONFIG_SYS_NS16550
Tom Rix660888b2009-05-31 12:44:37 +020089#define CONFIG_SYS_NS16550_REG_SIZE (-2)
Tom Rix376aee72009-05-15 23:48:36 +020090#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Tom Rix660888b2009-05-31 12:44:37 +020091#define CONFIG_BAUDRATE 115200
92#define CONFIG_SYS_BAUDRATE_TABLE {115200}
Tom Rix376aee72009-05-15 23:48:36 +020093
94/* allow to overwrite serial and ethaddr */
95#define CONFIG_ENV_OVERWRITE
Tom Rix660888b2009-05-31 12:44:37 +020096
Tom Rix376aee72009-05-15 23:48:36 +020097#define CONFIG_MMC 1
98#define CONFIG_OMAP3_MMC 1
99#define CONFIG_DOS_PARTITION 1
100
Nishanth Menon30563a02009-11-07 10:51:24 -0500101/* DDR - I use Micron DDR */
102#define CONFIG_OMAP3_MICRON_DDR 1
103
Tom Rix83ae6982009-05-31 12:44:39 +0200104/* Status LED */
105#define CONFIG_STATUS_LED 1 /* Status LED enabled */
106#define CONFIG_BOARD_SPECIFIC_LED 1
107#define STATUS_LED_BLUE 0
108#define STATUS_LED_RED 1
109/* Blue */
110#define STATUS_LED_BIT STATUS_LED_BLUE
111#define STATUS_LED_STATE STATUS_LED_ON
112#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
113/* Red */
114#define STATUS_LED_BIT1 STATUS_LED_RED
115#define STATUS_LED_STATE1 STATUS_LED_OFF
116#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
117/* Optional value */
118#define STATUS_LED_BOOT STATUS_LED_BIT
119
Tom Rix0c9520e2009-05-29 18:57:32 -0500120/* GPIO banks */
121#ifdef CONFIG_STATUS_LED
122#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
123#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
124#endif
125#define CONFIG_OMAP3_GPIO_3 /* board revision */
126#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
127
Tom Rix376aee72009-05-15 23:48:36 +0200128/* commands to include */
129#include <config_cmd_default.h>
130
131#define CONFIG_CMD_FAT /* FAT support */
132#define CONFIG_CMD_I2C /* I2C serial bus support */
133#define CONFIG_CMD_MMC /* MMC support */
134#define CONFIG_CMD_NAND /* NAND support */
135#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
136
137#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
138#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
139#undef CONFIG_CMD_IMI /* iminfo */
140#undef CONFIG_CMD_IMLS /* List all found images */
141#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
142#undef CONFIG_CMD_NFS /* NFS support */
143
144#define CONFIG_SYS_NO_FLASH
Tom Rix0297ec72009-09-29 10:19:49 -0400145#define CONFIG_HARD_I2C 1
Tom Rix376aee72009-05-15 23:48:36 +0200146#define CONFIG_SYS_I2C_SPEED 100000
147#define CONFIG_SYS_I2C_SLAVE 1
148#define CONFIG_SYS_I2C_BUS 0
149#define CONFIG_SYS_I2C_BUS_SELECT 1
150#define CONFIG_DRIVER_OMAP34XX_I2C 1
151
152/*
Tom Rixcd782632009-06-28 12:52:29 -0500153 * TWL4030
154 */
155#define CONFIG_TWL4030_POWER 1
Tom Rix2c155132009-06-28 12:52:30 -0500156#define CONFIG_TWL4030_LED 1
Tom Rixcd782632009-06-28 12:52:29 -0500157
158/*
Tom Rix376aee72009-05-15 23:48:36 +0200159 * Board NAND Info.
160 */
161#define CONFIG_NAND_OMAP_GPMC
162#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
163 /* to access nand */
164#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
165 /* to access nand at */
166 /* CS0 */
167#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
168#define CONFIG_SYS_MAX_NAND_DEVICE 1
169
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200170#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
171
Tom Rix376aee72009-05-15 23:48:36 +0200172/* Environment information */
173#define CONFIG_BOOTDELAY 10
174
175/*
176 * Miscellaneous configurable options
177 */
178
179#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # "
180#define CONFIG_SYS_LONGHELP
181#define CONFIG_SYS_CBSIZE 256
182#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
183 sizeof(CONFIG_SYS_PROMPT) + 16)
184#define CONFIG_SYS_MAXARGS 16
185#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
186/* Memtest from start of memory to 31MB */
187#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
188#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)
189/* The default load address is the start of memory */
190#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
191/* everything, incl board info, in Hz */
192#undef CONFIG_SYS_CLKS_IN_HZ
193/*
194 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
195 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
196 */
197#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
198#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
199#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
200
201/*-----------------------------------------------------------------------
202 * Stack sizes
203 *
204 * The stack sizes are set up in start.S using these settings
205 */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400206#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Tom Rix376aee72009-05-15 23:48:36 +0200207#ifdef CONFIG_USE_IRQ
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400208#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
209#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
Tom Rix376aee72009-05-15 23:48:36 +0200210#endif
211
212/*-----------------------------------------------------------------------
213 * Physical Memory Map
214 */
215#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
216#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400217#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
Tom Rix376aee72009-05-15 23:48:36 +0200218#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
219
220/* SDRAM Bank Allocation method */
221#define SDRC_R_B_C 1
222
223/*-----------------------------------------------------------------------
224 * FLASH and environment organization
225 */
226
227/* **** PISMO SUPPORT *** */
228
229/* Configure the PISMO */
230#define PISMO1_NAND_SIZE GPMC_SIZE_128M
231#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
232
233#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
234 /* one chip */
235#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400236#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Tom Rix376aee72009-05-15 23:48:36 +0200237
238#define CONFIG_SYS_FLASH_BASE boot_flash_base
239
240/* Monitor at start of flash */
241#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
242
243#define CONFIG_ENV_IS_IN_NAND 1
244#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
245
246#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
247#define CONFIG_ENV_OFFSET boot_flash_off
248#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
249
250/*-----------------------------------------------------------------------
251 * CFI FLASH driver setup
252 */
253/* timeout values are in ticks */
254#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
255#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
256
257#ifndef __ASSEMBLY__
Dirk Behme97a099e2009-08-08 09:30:21 +0200258extern struct gpmc *gpmc_cfg;
Tom Rix376aee72009-05-15 23:48:36 +0200259extern unsigned int boot_flash_base;
260extern volatile unsigned int boot_flash_env_addr;
261extern unsigned int boot_flash_off;
262extern unsigned int boot_flash_sec;
263extern unsigned int boot_flash_type;
264#endif
265
266#endif /* __CONFIG_H */