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Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * Socrates
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/* High Level Configuration Options */
37#define CONFIG_BOOKE 1 /* BOOKE */
38#define CONFIG_E500 1 /* BOOKE e500 family */
39#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
40#define CONFIG_MPC8544 1
41#define CONFIG_SOCRATES 1
42
43#define CONFIG_PCI
44
45#define CONFIG_TSEC_ENET /* tsec ethernet support */
46
47#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
48
49#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
50
51/*
52 * Only possible on E500 Version 2 or newer cores.
53 */
54#define CONFIG_ENABLE_36BIT_PHYS 1
55
56/*
57 * sysclk for MPC85xx
58 *
59 * Two valid values are:
60 * 33000000
61 * 66000000
62 *
63 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
64 * is likely the desired value here, so that is now the default.
65 * The board, however, can run at 66MHz. In any event, this value
66 * must match the settings of some switches. Details can be found
67 * in the README.mpc85xxads.
68 */
69
70#ifndef CONFIG_SYS_CLK_FREQ
71#define CONFIG_SYS_CLK_FREQ 66666666
72#endif
73
74/*
75 * These can be toggled for performance analysis, otherwise use default.
76 */
77#define CONFIG_L2_CACHE /* toggle L2 cache */
78#define CONFIG_BTB /* toggle branch predition */
79#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
80
81#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
82
83#undef CFG_DRAM_TEST /* memory test, takes time */
84#define CFG_MEMTEST_START 0x00000000
85#define CFG_MEMTEST_END 0x10000000
86
87/*
88 * Base addresses -- Note these are effective addresses where the
89 * actual resources get mapped (not physical addresses)
90 */
91#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
92#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
93#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
94#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
95
96/*
97 * DDR Setup
98 */
99#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
100#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
101
102#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
103
104/* Hardcoded values, to use instead of SPD */
105#define CFG_DDR_CS0_BNDS 0x0000000f
106#define CFG_DDR_CS0_CONFIG 0x80010102
107#define CFG_DDR_TIMING_0 0x00260802
108#define CFG_DDR_TIMING_1 0x3935D322
109#define CFG_DDR_TIMING_2 0x14904CC8
110#define CFG_DDR_MODE 0x00480432
111#define CFG_DDR_INTERVAL 0x030C0100
112#define CFG_DDR_CONFIG_2 0x04400000
113#define CFG_DDR_CONFIG 0xC3008000
114#define CFG_DDR_CLK_CONTROL 0x03800000
115#define CFG_SDRAM_SIZE 256 /* in Megs */
116
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200117#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
118#define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */
119#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200120
121/*
122 * Flash on the Local Bus
123 */
124/*
125 * Flash on the LocalBus
126 */
127#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
128
129#define CFG_FLASH0 0xFE000000
130#define CFG_FLASH1 0xFC000000
131#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
132
133#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
134#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
135
136#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
137#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
138#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
139#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
140
141#define CFG_FLASH_CFI /* flash is CFI compat. */
142#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
143#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
144
145#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200146#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200147#undef CFG_FLASH_CHECKSUM
148#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150
151#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
152
153#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
154#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
155#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
156#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
157
158#define CONFIG_L1_INIT_RAM
159#define CFG_INIT_RAM_LOCK 1
160#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
161#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
162
163#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
164#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
165#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
166
167#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
168#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
169
170/* Serial Port */
171
172#define CONFIG_CONS_INDEX 1
173#undef CONFIG_SERIAL_SOFTWARE_FIFO
174#define CFG_NS16550
175#define CFG_NS16550_SERIAL
176#define CFG_NS16550_REG_SIZE 1
177#define CFG_NS16550_CLK get_bus_freq(0)
178
179#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
180#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
181
182#define CONFIG_BAUDRATE 115200
183
184#define CFG_BAUDRATE_TABLE \
185 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
186
187#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
188#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
189#ifdef CFG_HUSH_PARSER
190#define CFG_PROMPT_HUSH_PS2 "> "
191#endif
192
193
194/*
195 * I2C
196 */
197#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
198#define CONFIG_HARD_I2C /* I2C with hardware support */
199#undef CONFIG_SOFT_I2C /* I2C bit-banged */
200#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
201#define CFG_I2C_SLAVE 0x7F
202#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
203#define CFG_I2C_OFFSET 0x3000
204
205/* I2C RTC */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200206#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
207#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200208
209/* RapidIO MMU */
210#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
211#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
212#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
213
214/*
215 * General PCI
216 * Memory space is mapped 1-1.
217 */
218#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
219
220
221#define CFG_PCI1_MEM_BASE 0x80000000
222#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
223#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
224#define CFG_PCI1_IO_BASE 0xE2000000
225#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
226#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
227
228#if defined(CONFIG_PCI)
229
230#define CONFIG_PCI_PNP /* do pci plug-and-play */
231
232#define CONFIG_EEPRO100
233#undef CONFIG_TULIP
234
235#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
236#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
237
238#endif /* CONFIG_PCI */
239
240
241#define CONFIG_NET_MULTI 1
242#define CONFIG_MII 1 /* MII PHY management */
243#define CONFIG_TSEC1 1
244#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200245#define CONFIG_TSEC3 1
246#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200247#undef CONFIG_MPC85XX_FEC
248
249#define TSEC1_PHY_ADDR 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200250#define TSEC3_PHY_ADDR 1
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200251
252#define TSEC1_PHYIDX 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200253#define TSEC3_PHYIDX 0
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200254#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200255#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200256
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200257/* Options are: TSEC[0,1] */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200258#define CONFIG_ETHPRIME "TSEC0"
259#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
260
Sergei Poselenove18575d2008-05-07 15:10:49 +0200261#define CONFIG_HAS_ETH0
262#define CONFIG_HAS_ETH1
263
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200264/*
265 * Environment
266 */
267#define CFG_ENV_IS_IN_FLASH 1
268#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
269#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
270#define CFG_ENV_SIZE 0x4000
271#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
272#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
273
274#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
275#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
276
277#define CONFIG_TIMESTAMP /* Print image info with ts */
278
279
280/*
281 * BOOTP options
282 */
283#define CONFIG_BOOTP_BOOTFILESIZE
284#define CONFIG_BOOTP_BOOTPATH
285#define CONFIG_BOOTP_GATEWAY
286#define CONFIG_BOOTP_HOSTNAME
287
288
289/*
290 * Command line configuration.
291 */
292#include <config_cmd_default.h>
293
294#define CONFIG_CMD_DATE
295#define CONFIG_CMD_DHCP
296#undef CONFIG_CMD_DTT
297#undef CONFIG_CMD_EEPROM
298#define CONFIG_CMD_I2C
299#define CONFIG_CMD_MII
300#define CONFIG_CMD_NFS
301#define CONFIG_CMD_PING
302#undef CONFIG_CMD_RTC
303#define CONFIG_CMD_SNTP
304
305
306#if defined(CONFIG_PCI)
307 #define CONFIG_CMD_PCI
308#endif
309
310
311#undef CONFIG_WATCHDOG /* watchdog disabled */
312
313/*
314 * Miscellaneous configurable options
315 */
316#define CFG_LONGHELP /* undef to save memory */
317#define CFG_LOAD_ADDR 0x2000000 /* default load address */
318#define CFG_PROMPT "=> " /* Monitor Command Prompt */
319
320#if defined(CONFIG_CMD_KGDB)
321 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
322#else
323 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
324#endif
325
326#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
327#define CFG_MAXARGS 16 /* max number of command args */
328#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
329#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
330
331/*
332 * For booting Linux, the board info and command line data
333 * have to be in the first 8 MB of memory, since this is
334 * the maximum mapped by the Linux kernel during initialization.
335 */
336#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
337
338/*
339 * Internal Definitions
340 *
341 * Boot Flags
342 */
343#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
344#define BOOTFLAG_WARM 0x02 /* Software reboot */
345
346#if defined(CONFIG_CMD_KGDB)
347#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
348#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
349#endif
350
351
352#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
353
354#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
355
356#define CONFIG_PREBOOT "echo;" \
357 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
358 "echo"
359
360#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
361
362#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200363 "bootfile=/tftpboot/socrates/uImage\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200364 "netdev=eth0\0" \
365 "consdev=ttyS0\0" \
366 "nfsargs=setenv bootargs root=/dev/nfs rw " \
367 "nfsroot=$serverip:$rootpath\0" \
368 "ramargs=setenv bootargs root=/dev/ram rw\0" \
369 "addip=setenv bootargs $bootargs " \
370 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
371 ":$hostname:$netdev:off panic=1\0" \
372 "addcons=setenv bootargs $bootargs " \
373 "console=$consdev,$baudrate\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200374 "flash_self=run ramargs addip addcons;" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200375 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
376 "flash_nfs=run nfsargs addip addcons;" \
377 "bootm ${kernel_addr} - ${fdt_addr}\0" \
378 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
379 "tftp ${fdt_addr_r} ${fdt_file}; " \
380 "run nfsargs addip addcons;" \
381 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
382 "fdt_file=socrates/socrates.dtb\0" \
383 "fdt_addr_r=B00000\0" \
384 "fdt_addr=FC1E0000\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200385 "rootpath=/opt/eldk/ppc_85xx\0" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200386 "kernel_addr=FC000000\0" \
387 "kernel_addr_r=200000\0" \
388 "ramdisk_addr=FC200000\0" \
389 "ramdisk_addr_r=400000\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200390 "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
391 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
392 "cp.b 100000 fffc0000 40000;" \
393 "setenv filesize;saveenv\0" \
394 "upd=run load update\0" \
395 ""
396#define CONFIG_BOOTCOMMAND "run flash_self"
397
Sergei Poselenove18575d2008-05-07 15:10:49 +0200398/* pass open firmware flat tree */
399#define CONFIG_OF_LIBFDT 1
400#define CONFIG_OF_BOARD_SETUP 1
401
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200402#endif /* __CONFIG_H */