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Ramneek Mehreshba92ee02015-05-29 14:47:19 +05301/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * FSL USB HOST xHCI Controller
5 *
6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#ifndef _ASM_ARCH_XHCI_FSL_H_
12#define _ASM_ARCH_XHCI_FSL_H_
13
14/* Default to the FSL XHCI defines */
15#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
16#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
17#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
18#define USB3_PHY_RX_POWERON BIT(14)
19#define USB3_PHY_TX_POWERON BIT(15)
20#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
21#define USB3_PWRCTL_CLK_CMD_SHIFT 14
22#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
23
24/* USBOTGSS_WRAPPER definitions */
25#define USBOTGSS_WRAPRESET BIT(17)
26#define USBOTGSS_DMADISABLE BIT(16)
27#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
28#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
29#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
30#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
31#define USBOTGSS_IDLEMODE_SMRT BIT(3)
32#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
33
34/* USBOTGSS_IRQENABLE_SET_0 bit */
35#define USBOTGSS_COREIRQ_EN BIT(1)
36
37/* USBOTGSS_IRQENABLE_SET_1 bits */
38#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
39#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
40#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
41#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
42#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
43#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
44#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
45#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
46#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
47#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
48
49struct fsl_xhci {
50 struct xhci_hccr *hcd;
51 struct dwc3 *dwc3_reg;
52};
53
Nikhil Badola909a1ab2015-06-23 09:18:03 +053054#if defined(CONFIG_LS102XA)
55#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
56#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
Nikhil Badola2f473242015-06-23 09:18:20 +053057#elif defined(CONFIG_LS2085A)
58#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
59#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
Nikhil Badola909a1ab2015-06-23 09:18:03 +053060#endif
61
62#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
63 CONFIG_SYS_FSL_XHCI_USB2_ADDR}
Ramneek Mehreshba92ee02015-05-29 14:47:19 +053064#endif /* _ASM_ARCH_XHCI_FSL_H_ */