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TsiChung Liew6d33c6a2008-07-23 17:11:47 -05001/*
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _M5253DEMO_H
25#define _M5253DEMO_H
26
27#define CONFIG_MCF52x2 /* define processor family */
28#define CONFIG_M5253 /* define processor type */
29#define CONFIG_M5253DEMO /* define board type */
30
31#define CONFIG_MCFTMR
32
33#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050035#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050037
38#undef CONFIG_WATCHDOG /* disable watchdog */
39
40#define CONFIG_BOOTDELAY 5
41
42/* Configuration for environment
43 * Environment is embedded in u-boot in the second sector of the flash
44 */
45#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020046# define CONFIG_ENV_OFFSET 0x4000
47# define CONFIG_ENV_SECT_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020048# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050049#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020051# define CONFIG_ENV_SECT_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020052# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050053#endif
54
55/*
56 * Command line configuration.
57 */
58#include <config_cmd_default.h>
59
60#define CONFIG_CMD_LOADB
61#define CONFIG_CMD_LOADS
62#define CONFIG_CMD_EXT2
63#define CONFIG_CMD_FAT
64#define CONFIG_CMD_IDE
65#define CONFIG_CMD_MEMORY
66#define CONFIG_CMD_MISC
67#define CONFIG_CMD_PING
68
69#ifdef CONFIG_CMD_IDE
70/* ATA */
71# define CONFIG_DOS_PARTITION
72# define CONFIG_MAC_PARTITION
73# define CONFIG_IDE_RESET 1
74# define CONFIG_IDE_PREINIT 1
75# define CONFIG_ATAPI
76# undef CONFIG_LBA48
77
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078# define CONFIG_SYS_IDE_MAXBUS 1
79# define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
82# define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
85# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
86# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
87# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050088# define _IO_BASE 0
89#endif
90
91#define CONFIG_DRIVER_DM9000
92#ifdef CONFIG_DRIVER_DM9000
TsiChung Liew012522f2008-10-21 10:03:07 +000093# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050094# define DM9000_IO CONFIG_DM9000_BASE
95# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
96# undef CONFIG_DM9000_DEBUG
97
98# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
99# define CONFIG_IPADDR 10.82.121.249
100# define CONFIG_NETMASK 255.255.252.0
101# define CONFIG_SERVERIP 10.82.120.80
102# define CONFIG_GATEWAYIP 10.82.123.254
103# define CONFIG_OVERWRITE_ETHADDR_ONCE
104
105# define CONFIG_EXTRA_ENV_SETTINGS \
106 "netdev=eth0\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500108 "loadaddr=10000\0" \
109 "u-boot=u-boot.bin\0" \
110 "load=tftp ${loadaddr) ${u-boot}\0" \
111 "upd=run load; run prog\0" \
112 "prog=prot off 0 2ffff;" \
113 "era 0 2ffff;" \
114 "cp.b ${loadaddr} 0 ${filesize};" \
115 "save\0" \
116 ""
117#endif
118
119#define CONFIG_HOSTNAME M5253DEMO
120
TsiChung Lieweec567a2008-08-19 03:01:19 +0600121/* I2C */
122#define CONFIG_FSL_I2C
123#define CONFIG_HARD_I2C /* I2C with hw support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_I2C_SPEED 80000
125#define CONFIG_SYS_I2C_SLAVE 0x7F
126#define CONFIG_SYS_I2C_OFFSET 0x00000280
127#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
128#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
129#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
130#define CONFIG_SYS_I2C_PINMUX_SET (0)
TsiChung Lieweec567a2008-08-19 03:01:19 +0600131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_PROMPT "=> "
133#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500134
135#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500137#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500139#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
141#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
142#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x00100000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_MEMTEST_START 0x400
147#define CONFIG_SYS_MEMTEST_END 0x380000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_HZ 1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
152#define CONFIG_SYS_FAST_CLK
153#ifdef CONFIG_SYS_FAST_CLK
154# define CONFIG_SYS_PLLCR 0x1243E054
155# define CONFIG_SYS_CLK 140000000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500156#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157# define CONFIG_SYS_PLLCR 0x135a4140
158# define CONFIG_SYS_CLK 70000000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500159#endif
160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
168#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500169
170/*
171 * Definitions for initial stack pointer and data area (in DPRAM)
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
174#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
175#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
176#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
177#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500178
179/*
180 * Start addresses for the final memory configuration
181 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500186
187#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188# define CONFIG_SYS_MONITOR_BASE 0x20000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500189#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500191#endif
192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_MONITOR_LEN 0x40000
194#define CONFIG_SYS_MALLOC_LEN (256 << 10)
195#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500196
197/*
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization ??
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500203
204/* FLASH organization */
TsiChung Liew012522f2008-10-21 10:03:07 +0000205#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
207#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
208#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500209
210#define FLASH_SST6401B 0x200
211#define SST_ID_xF6401B 0x236D236D
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#undef CONFIG_SYS_FLASH_CFI
214#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500215/*
216 * Unable to use CFI driver, due to incompatible sector erase command by SST.
217 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
218 * 0x30 is block erase in SST
219 */
Jean-Christophe PLAGNIOL-VILLARD0de0afb2008-08-15 18:32:41 +0200220# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221# define CONFIG_SYS_FLASH_SIZE 0x800000
222# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500223# define CONFIG_FLASH_CFI_LEGACY
224#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225# define CONFIG_SYS_SST_SECT 2048
226# define CONFIG_SYS_SST_SECTSZ 0x1000
227# define CONFIG_SYS_FLASH_WRITE_TOUT 500
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500228#endif
229
230/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500232
233/* Port configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_FECI2C 0xF0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500235
TsiChung Liew012522f2008-10-21 10:03:07 +0000236#define CONFIG_SYS_CS0_BASE 0xFF800000
237#define CONFIG_SYS_CS0_MASK 0x007F0021
238#define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500239
TsiChung Liew012522f2008-10-21 10:03:07 +0000240#define CONFIG_SYS_CS1_BASE 0xE0000000
241#define CONFIG_SYS_CS1_MASK 0x00000001
242#define CONFIG_SYS_CS1_CTRL 0x00003DD8
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500243
244/*-----------------------------------------------------------------------
245 * Port configuration
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
248#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
249#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
250#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
251#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
252#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
253#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500254
255#endif /* _M5253DEMO_H */