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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Fabio Estevam0c5e2662013-09-26 22:59:25 -03002/*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam0c5e2662013-09-26 22:59:25 -03006 */
7
8#include <asm/arch/clock.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/iomux.h>
Giuseppe Pagano078813d2013-11-15 17:42:51 +010011#include <malloc.h>
Fabio Estevam0c5e2662013-09-26 22:59:25 -030012#include <asm/arch/mx6-pins.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090013#include <linux/errno.h>
Fabio Estevam0c5e2662013-09-26 22:59:25 -030014#include <asm/gpio.h>
Stefano Babic552a8482017-06-29 10:16:06 +020015#include <asm/mach-imx/iomux-v3.h>
16#include <asm/mach-imx/sata.h>
Fabio Estevam0c5e2662013-09-26 22:59:25 -030017#include <mmc.h>
18#include <fsl_esdhc.h>
19#include <asm/arch/crm_regs.h>
20#include <asm/io.h>
21#include <asm/arch/sys_proto.h>
Giuseppe Pagano078813d2013-11-15 17:42:51 +010022#include <micrel.h>
23#include <miiphy.h>
24#include <netdev.h>
Fabio Estevam0c5e2662013-09-26 22:59:25 -030025
26DECLARE_GLOBAL_DATA_PTR;
27
28#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
29 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
30 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
31
Giuseppe Pagano078813d2013-11-15 17:42:51 +010032#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
34
Fabio Estevam0c5e2662013-09-26 22:59:25 -030035#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
36 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39#define WDT_EN IMX_GPIO_NR(5, 4)
40#define WDT_TRG IMX_GPIO_NR(3, 19)
41
42int dram_init(void)
43{
vpeter478506c22015-08-03 12:49:05 +020044 gd->ram_size = imx_ddr_size();
Fabio Estevam0c5e2662013-09-26 22:59:25 -030045
46 return 0;
47}
48
49static iomux_v3_cfg_t const uart2_pads[] = {
vpeter478506c22015-08-03 12:49:05 +020050 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
51 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
Fabio Estevam0c5e2662013-09-26 22:59:25 -030052};
53
54static iomux_v3_cfg_t const usdhc3_pads[] = {
vpeter478506c22015-08-03 12:49:05 +020055 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
56 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
Fabio Estevam0c5e2662013-09-26 22:59:25 -030061};
62
63static iomux_v3_cfg_t const wdog_pads[] = {
vpeter478506c22015-08-03 12:49:05 +020064 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
65 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
Fabio Estevam0c5e2662013-09-26 22:59:25 -030066};
67
Giuseppe Pagano078813d2013-11-15 17:42:51 +010068int mx6_rgmii_rework(struct phy_device *phydev)
69{
70 /*
71 * Bug: Apparently uDoo does not works with Gigabit switches...
72 * Limiting speed to 10/100Mbps, and setting master mode, seems to
73 * be the only way to have a successfull PHY auto negotiation.
74 * How to fix: Understand why Linux kernel do not have this issue.
75 */
76 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
77
78 /* control data pad skew - devaddr = 0x02, register = 0x04 */
79 ksz9031_phy_extended_write(phydev, 0x02,
80 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
81 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
82 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
83 ksz9031_phy_extended_write(phydev, 0x02,
84 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
85 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
86 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
87 ksz9031_phy_extended_write(phydev, 0x02,
88 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
89 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
90 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
91 ksz9031_phy_extended_write(phydev, 0x02,
92 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
93 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
94 return 0;
95}
96
97static iomux_v3_cfg_t const enet_pads1[] = {
vpeter478506c22015-08-03 12:49:05 +020098 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
99 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
106 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100108 /* RGMII reset */
vpeter478506c22015-08-03 12:49:05 +0200109 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100110 /* Ethernet power supply */
vpeter478506c22015-08-03 12:49:05 +0200111 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100112 /* pin 32 - 1 - (MODE0) all */
vpeter478506c22015-08-03 12:49:05 +0200113 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100114 /* pin 31 - 1 - (MODE1) all */
vpeter478506c22015-08-03 12:49:05 +0200115 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100116 /* pin 28 - 1 - (MODE2) all */
vpeter478506c22015-08-03 12:49:05 +0200117 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100118 /* pin 27 - 1 - (MODE3) all */
vpeter478506c22015-08-03 12:49:05 +0200119 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100120 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
vpeter478506c22015-08-03 12:49:05 +0200121 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100122};
123
124static iomux_v3_cfg_t const enet_pads2[] = {
vpeter478506c22015-08-03 12:49:05 +0200125 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
126 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
127 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
128 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
129 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100130};
131
132static void setup_iomux_enet(void)
133{
vpeter478506c22015-08-03 12:49:05 +0200134 SETUP_IOMUX_PADS(enet_pads1);
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100135 udelay(20);
136 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
137
138 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
139
140 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
141 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
142 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
143 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
144 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
145 udelay(1000);
146
147 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
148
149 /* Need 100ms delay to exit from reset. */
150 udelay(1000 * 100);
151
152 gpio_free(IMX_GPIO_NR(6, 24));
153 gpio_free(IMX_GPIO_NR(6, 25));
154 gpio_free(IMX_GPIO_NR(6, 27));
155 gpio_free(IMX_GPIO_NR(6, 28));
156 gpio_free(IMX_GPIO_NR(6, 29));
157
vpeter478506c22015-08-03 12:49:05 +0200158 SETUP_IOMUX_PADS(enet_pads2);
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100159}
160
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300161static void setup_iomux_uart(void)
162{
vpeter478506c22015-08-03 12:49:05 +0200163 SETUP_IOMUX_PADS(uart2_pads);
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300164}
165
166static void setup_iomux_wdog(void)
167{
vpeter478506c22015-08-03 12:49:05 +0200168 SETUP_IOMUX_PADS(wdog_pads);
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300169 gpio_direction_output(WDT_TRG, 0);
170 gpio_direction_output(WDT_EN, 1);
Giuseppe Paganodb6801d2013-11-15 17:42:54 +0100171 gpio_direction_input(WDT_TRG);
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300172}
173
174static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
175
176int board_mmc_getcd(struct mmc *mmc)
177{
178 return 1; /* Always present */
179}
180
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100181int board_eth_init(bd_t *bis)
182{
183 uint32_t base = IMX_FEC_BASE;
184 struct mii_dev *bus = NULL;
185 struct phy_device *phydev = NULL;
186 int ret;
187
188 setup_iomux_enet();
189
190#ifdef CONFIG_FEC_MXC
191 bus = fec_get_miibus(base, -1);
192 if (!bus)
Fabio Estevam84c311f2015-09-11 13:32:50 -0300193 return -EINVAL;
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100194 /* scan phy 4,5,6,7 */
195 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
196
197 if (!phydev) {
Fabio Estevam84c311f2015-09-11 13:32:50 -0300198 ret = -EINVAL;
199 goto free_bus;
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100200 }
201 printf("using phy at %d\n", phydev->addr);
202 ret = fec_probe(bis, -1, base, bus, phydev);
Fabio Estevam84c311f2015-09-11 13:32:50 -0300203 if (ret)
204 goto free_phydev;
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100205#endif
206 return 0;
Fabio Estevam84c311f2015-09-11 13:32:50 -0300207
208free_phydev:
209 free(phydev);
210free_bus:
211 free(bus);
212 return ret;
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100213}
214
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300215int board_mmc_init(bd_t *bis)
216{
vpeter478506c22015-08-03 12:49:05 +0200217 SETUP_IOMUX_PADS(usdhc3_pads);
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300218 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
219 usdhc_cfg.max_bus_width = 4;
220
221 return fsl_esdhc_initialize(bis, &usdhc_cfg);
222}
223
224int board_early_init_f(void)
225{
226 setup_iomux_wdog();
227 setup_iomux_uart();
228
229 return 0;
230}
231
Giuseppe Pagano078813d2013-11-15 17:42:51 +0100232int board_phy_config(struct phy_device *phydev)
233{
234 mx6_rgmii_rework(phydev);
235 if (phydev->drv->config)
236 phydev->drv->config(phydev);
237
238 return 0;
239}
240
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300241int board_init(void)
242{
243 /* address of boot parameters */
244 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
245
Simon Glass10e40d52017-06-14 21:28:25 -0600246#ifdef CONFIG_SATA
Fabio Estevam0d6a41e2017-10-15 11:21:07 -0200247 setup_sata();
vpeter478506c22015-08-03 12:49:05 +0200248#endif
249 return 0;
250}
251
252int board_late_init(void)
253{
254#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
255 if (is_cpu_type(MXC_CPU_MX6Q))
Simon Glass382bee52017-08-03 12:22:09 -0600256 env_set("board_rev", "MX6Q");
vpeter478506c22015-08-03 12:49:05 +0200257 else
Simon Glass382bee52017-08-03 12:22:09 -0600258 env_set("board_rev", "MX6DL");
Giuseppe Pagano98d01222013-11-28 12:32:49 +0100259#endif
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300260 return 0;
261}
262
263int checkboard(void)
264{
vpeter478506c22015-08-03 12:49:05 +0200265 if (is_cpu_type(MXC_CPU_MX6Q))
266 puts("Board: Udoo Quad\n");
267 else
268 puts("Board: Udoo DualLite\n");
Fabio Estevam0c5e2662013-09-26 22:59:25 -0300269
270 return 0;
271}