Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013 Xilinx Inc. |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <malloc.h> |
| 10 | #include <asm/arch/hardware.h> |
Michal Simek | 3b5b599 | 2014-04-25 13:48:08 +0200 | [diff] [blame] | 11 | #include <asm/arch/sys_proto.h> |
Soren Brinkmann | 97598fc | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 12 | #include <asm/arch/clk.h> |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 13 | |
| 14 | #define SLCR_LOCK_MAGIC 0x767B |
| 15 | #define SLCR_UNLOCK_MAGIC 0xDF0D |
| 16 | |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 17 | #define SLCR_IDCODE_MASK 0x1F000 |
| 18 | #define SLCR_IDCODE_SHIFT 12 |
| 19 | |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 20 | static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ |
| 21 | |
| 22 | void zynq_slcr_lock(void) |
| 23 | { |
Michal Simek | 2da7a74 | 2013-08-30 07:26:08 +0200 | [diff] [blame^] | 24 | if (!slcr_lock) { |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 25 | writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); |
Michal Simek | 2da7a74 | 2013-08-30 07:26:08 +0200 | [diff] [blame^] | 26 | slcr_lock = 1; |
| 27 | } |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | void zynq_slcr_unlock(void) |
| 31 | { |
Michal Simek | 2da7a74 | 2013-08-30 07:26:08 +0200 | [diff] [blame^] | 32 | if (slcr_lock) { |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 33 | writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); |
Michal Simek | 2da7a74 | 2013-08-30 07:26:08 +0200 | [diff] [blame^] | 34 | slcr_lock = 0; |
| 35 | } |
Michal Simek | 59c651f | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | /* Reset the entire system */ |
| 39 | void zynq_slcr_cpu_reset(void) |
| 40 | { |
| 41 | /* |
| 42 | * Unlock the SLCR then reset the system. |
| 43 | * Note that this seems to require raw i/o |
| 44 | * functions or there's a lockup? |
| 45 | */ |
| 46 | zynq_slcr_unlock(); |
| 47 | |
| 48 | /* |
| 49 | * Clear 0x0F000000 bits of reboot status register to workaround |
| 50 | * the FSBL not loading the bitstream after soft-reboot |
| 51 | * This is a temporary solution until we know more. |
| 52 | */ |
| 53 | clrbits_le32(&slcr_base->reboot_status, 0xF000000); |
| 54 | |
| 55 | writel(1, &slcr_base->pss_rst_ctrl); |
| 56 | } |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 57 | |
| 58 | /* Setup clk for network */ |
Soren Brinkmann | 97598fc | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 59 | void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 60 | { |
Soren Brinkmann | 97598fc | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 61 | int ret; |
| 62 | |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 63 | zynq_slcr_unlock(); |
| 64 | |
| 65 | if (gem_id > 1) { |
| 66 | printf("Non existing GEM id %d\n", gem_id); |
| 67 | goto out; |
| 68 | } |
| 69 | |
Soren Brinkmann | 97598fc | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 70 | ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate); |
| 71 | if (ret) |
| 72 | goto out; |
| 73 | |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 74 | if (gem_id) { |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 75 | /* Configure GEM_RCLK_CTRL */ |
Soren Brinkmann | 1cd46ed | 2013-11-21 13:39:00 -0800 | [diff] [blame] | 76 | writel(1, &slcr_base->gem1_rclk_ctrl); |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 77 | } else { |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 78 | /* Configure GEM_RCLK_CTRL */ |
Soren Brinkmann | 1cd46ed | 2013-11-21 13:39:00 -0800 | [diff] [blame] | 79 | writel(1, &slcr_base->gem0_rclk_ctrl); |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 80 | } |
Michal Simek | 39523be | 2013-05-08 15:37:28 +0200 | [diff] [blame] | 81 | udelay(100000); |
Michal Simek | 8024352 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 82 | out: |
| 83 | zynq_slcr_lock(); |
| 84 | } |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 85 | |
| 86 | void zynq_slcr_devcfg_disable(void) |
| 87 | { |
| 88 | zynq_slcr_unlock(); |
| 89 | |
Michal Simek | 6e04769 | 2014-03-27 10:06:43 +0100 | [diff] [blame] | 90 | /* Disable AXI interface by asserting FPGA resets */ |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 91 | writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); |
| 92 | |
| 93 | /* Set Level Shifters DT618760 */ |
| 94 | writel(0xA, &slcr_base->lvl_shftr_en); |
| 95 | |
| 96 | zynq_slcr_lock(); |
| 97 | } |
| 98 | |
| 99 | void zynq_slcr_devcfg_enable(void) |
| 100 | { |
| 101 | zynq_slcr_unlock(); |
| 102 | |
| 103 | /* Set Level Shifters DT618760 */ |
| 104 | writel(0xF, &slcr_base->lvl_shftr_en); |
| 105 | |
Michal Simek | 6e04769 | 2014-03-27 10:06:43 +0100 | [diff] [blame] | 106 | /* Enable AXI interface by de-asserting FPGA resets */ |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 107 | writel(0x0, &slcr_base->fpga_rst_ctrl); |
| 108 | |
| 109 | zynq_slcr_lock(); |
| 110 | } |
| 111 | |
Jagannadha Sutradharudu Teki | b3de924 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 112 | u32 zynq_slcr_get_boot_mode(void) |
| 113 | { |
| 114 | /* Get the bootmode register value */ |
| 115 | return readl(&slcr_base->boot_mode); |
| 116 | } |
| 117 | |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 118 | u32 zynq_slcr_get_idcode(void) |
| 119 | { |
| 120 | return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> |
| 121 | SLCR_IDCODE_SHIFT; |
| 122 | } |