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Michael Schwingenea99e8f2008-01-16 19:50:37 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * Configuration settings for the AcTux-1 board.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Michael Schwingenea99e8f2008-01-16 19:50:37 +01008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Michael Schwingenea99e8f2008-01-16 19:50:37 +010013#define CONFIG_IXP425 1
14#define CONFIG_ACTUX1 1
15
Marek Vasut8e807ec2012-03-06 00:45:35 +010016#define CONFIG_MACH_TYPE 1479
17
Michael Schwingenea99e8f2008-01-16 19:50:37 +010018#define CONFIG_DISPLAY_CPUINFO 1
19#define CONFIG_DISPLAY_BOARDINFO 1
20
Jean-Christophe PLAGNIOL-VILLARD930590f2009-01-31 09:10:48 +010021#define CONFIG_IXP_SERIAL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
Michael Schwingenea99e8f2008-01-16 19:50:37 +010023#define CONFIG_BAUDRATE 115200
24#define CONFIG_BOOTDELAY 3
25#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Michael Schwingen517c5df2011-05-23 00:00:04 +020026#define CONFIG_BOARD_EARLY_INIT_F 1
27#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds"
Michael Schwingenea99e8f2008-01-16 19:50:37 +010028
29/***************************************************************
30 * U-boot generic defines start here.
31 ***************************************************************/
Michael Schwingenea99e8f2008-01-16 19:50:37 +010032/*
33 * Size of malloc() pool
34 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Michael Schwingenea99e8f2008-01-16 19:50:37 +010036
37/* allow to overwrite serial and ethaddr */
38#define CONFIG_ENV_OVERWRITE
39
40/* Command line configuration. */
41#include <config_cmd_default.h>
42
43#define CONFIG_CMD_ELF
Michael Schwingen517c5df2011-05-23 00:00:04 +020044#ifdef CONFIG_PCI
45#define CONFIG_CMD_PCI
46#define CONFIG_PCI_PNP
47#define CONFIG_IXP_PCI
48#define CONFIG_PCI_SCAN_SHOW
49#define CONFIG_CMD_PCI_ENUM
50#endif
Michael Schwingenea99e8f2008-01-16 19:50:37 +010051
52#define CONFIG_BOOTCOMMAND "run boot_flash"
53/* enable passing of ATAGs */
54#define CONFIG_CMDLINE_TAG 1
55#define CONFIG_SETUP_MEMORY_TAGS 1
56#define CONFIG_INITRD_TAG 1
57#define CONFIG_REVISION_TAG 1
58
59#if defined(CONFIG_CMD_KGDB)
60# define CONFIG_KGDB_BAUDRATE 230400
61/* which serial port to use */
62# define CONFIG_KGDB_SER_INDEX 1
63#endif
64
65/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_LONGHELP
Michael Schwingenea99e8f2008-01-16 19:50:37 +010067/* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_CBSIZE 256
Michael Schwingenea99e8f2008-01-16 19:50:37 +010069/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Michael Schwingenea99e8f2008-01-16 19:50:37 +010071/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_MAXARGS 16
Michael Schwingenea99e8f2008-01-16 19:50:37 +010073/* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Michael Schwingenea99e8f2008-01-16 19:50:37 +010075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MEMTEST_START 0x00400000
77#define CONFIG_SYS_MEMTEST_END 0x00800000
Michael Schwingenea99e8f2008-01-16 19:50:37 +010078
Michael Schwingen517c5df2011-05-23 00:00:04 +020079/* timer clock - 2* OSC_IN system clock */
80#define CONFIG_IXP425_TIMER_CLK 66666666
Michael Schwingenea99e8f2008-01-16 19:50:37 +010081
82/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_LOAD_ADDR 0x00010000
Michael Schwingenea99e8f2008-01-16 19:50:37 +010084
85/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
Michael Schwingenea99e8f2008-01-16 19:50:37 +010087 115200, 230400 }
88#define CONFIG_SERIAL_RTS_ACTIVE 1
89
Michael Schwingenea99e8f2008-01-16 19:50:37 +010090/* Expansion bus settings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_EXP_CS0 0xbd113842
Michael Schwingenea99e8f2008-01-16 19:50:37 +010092
93/* SDRAM settings */
94#define CONFIG_NR_DRAM_BANKS 1
95#define PHYS_SDRAM_1 0x00000000
Michael Schwingen517c5df2011-05-23 00:00:04 +020096#define CONFIG_SYS_SDRAM_BASE 0x00000000
Michael Schwingenea99e8f2008-01-16 19:50:37 +010097
Michael Schwingen517c5df2011-05-23 00:00:04 +020098#ifdef CONFIG_RAM_32MB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099# define CONFIG_SYS_SDR_CONFIG 0x18
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100100# define PHYS_SDRAM_1_SIZE 0x02000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
102# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
103# define CONFIG_SYS_DRAM_SIZE 0x02000000
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100104#else /* 16MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105# define CONFIG_SYS_SDR_CONFIG 0x3A
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100106# define PHYS_SDRAM_1_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
108# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
109# define CONFIG_SYS_DRAM_SIZE 0x01000000
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100110#endif
111
112/* FLASH organization */
Michael Schwingen517c5df2011-05-23 00:00:04 +0200113#define CONFIG_SYS_TEXT_BASE 0x50000000
114#ifdef CONFIG_FLASH2X2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115# define CONFIG_SYS_MAX_FLASH_BANKS 2
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100116/* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117# define CONFIG_SYS_MAX_FLASH_SECT 40
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100118# define PHYS_FLASH_1 0x50000000
119# define PHYS_FLASH_2 0x50200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100121#endif
Michael Schwingen517c5df2011-05-23 00:00:04 +0200122#ifdef CONFIG_FLASH1X8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123# define CONFIG_SYS_MAX_FLASH_BANKS 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100124/* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125# define CONFIG_SYS_MAX_FLASH_SECT 140
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100126# define PHYS_FLASH_1 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100128#endif
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
131#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
132#define CONFIG_SYS_MONITOR_LEN (256 << 10)
Michael Schwingen517c5df2011-05-23 00:00:04 +0200133#define CONFIG_BOARD_SIZE_LIMIT 262144
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100134
135/* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200137#define CONFIG_FLASH_CFI_DRIVER
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100138/* no byte writes on IXP4xx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100140/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_FLASH_EMPTY_INFO
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100142
143/* Ethernet */
144
145/* include IXP4xx NPE support */
146#define CONFIG_IXP4XX_NPE 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100147/* NPE0 PHY address */
148#define CONFIG_PHY_ADDR 0
Michael Schwingen517c5df2011-05-23 00:00:04 +0200149/* NPE1 PHY address (HW Release E only) */
150#define CONFIG_PHY1_ADDR 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100151/* MII PHY management */
152#define CONFIG_MII 1
153/* Number of ethernet rx buffers & descriptors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_RX_ETH_BUFFER 16
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100155#define CONFIG_RESET_PHY_R 1
156
Michael Schwingen517c5df2011-05-23 00:00:04 +0200157#define CONFIG_HAS_ETH1 1
158
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100159#define CONFIG_CMD_DHCP
160#define CONFIG_CMD_NET
161#define CONFIG_CMD_MII
162#define CONFIG_CMD_PING
163#undef CONFIG_CMD_NFS
164
165/* BOOTP options */
166#define CONFIG_BOOTP_BOOTFILESIZE
167#define CONFIG_BOOTP_BOOTPATH
168#define CONFIG_BOOTP_GATEWAY
169#define CONFIG_BOOTP_HOSTNAME
170
171/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_CACHELINE_SIZE 32
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100173
174/*
175 * environment organization:
176 * one flash sector, embedded in uboot area (bottom bootblock flash)
177 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200178#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200179#define CONFIG_ENV_SIZE 0x2000
180#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_USE_PPCENV 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100182
Michael Schwingen517c5df2011-05-23 00:00:04 +0200183#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARDb4e2f892009-01-31 09:53:39 +0100184 "npe_ucode=50040000\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100185 "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
186 "kerneladdr=50050000\0" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200187 "kernelfile=actux1/uImage\0" \
188 "rootfile=actux1/rootfs\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100189 "rootaddr=50170000\0" \
190 "loadaddr=10000\0" \
191 "updateboot_ser=mw.b 10000 ff 40000;" \
192 " loady ${loadaddr};" \
193 " run eraseboot writeboot\0" \
194 "updateboot_net=mw.b 10000 ff 40000;" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200195 " tftp ${loadaddr} actux1/u-boot.bin;" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100196 " run eraseboot writeboot\0" \
197 "eraseboot=protect off 50000000 50003fff;" \
198 " protect off 50006000 5003ffff;" \
199 " erase 50000000 50003fff;" \
200 " erase 50006000 5003ffff\0" \
201 "writeboot=cp.b 10000 50000000 4000;" \
202 " cp.b 16000 50006000 3a000\0" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200203 "updateucode=loady;" \
204 " era ${npe_ucode} +${filesize};" \
205 " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100206 "updateroot=tftp ${loadaddr} ${rootfile};" \
207 " era ${rootaddr} +${filesize};" \
208 " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
209 "updatekern=tftp ${loadaddr} ${kernelfile};" \
210 " era ${kerneladdr} +${filesize};" \
211 " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
212 "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
213 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
214 "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
215 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200216 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100217 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
218 "boot_flash=run flashargs addtty addeth;" \
219 " bootm ${kerneladdr}\0" \
220 "boot_net=run netargs addtty addeth;" \
221 " tftpboot ${loadaddr} ${kernelfile};" \
222 " bootm\0"
223
Michael Schwingen517c5df2011-05-23 00:00:04 +0200224/* additions for new relocation code, must be added to all boards */
225#define CONFIG_SYS_INIT_SP_ADDR \
226 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
227
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100228#endif /* __CONFIG_H */