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gerrit.cesnet.cz / github / trini / u-boot / 2d16a1a6c9eeb30fa6828f048df06ee9807792d3 / . / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig
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York Sun9533acf2016-09-26 08:09:26 -0700[diff] [blame]1config ARCH_LS1012A
York Sun4a444172016-10-04 14:31:47 -0700[diff] [blame]2 bool
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]3 select FSL_LSCH2
York Sun24aaa092016-10-04 18:03:08 -0700[diff] [blame]4 select SYS_FSL_DDR_BE
York Sun9533acf2016-09-26 08:09:26 -0700[diff] [blame]5 select SYS_FSL_MMDC
York Sun0a37cf82016-09-26 08:09:27 -0700[diff] [blame]6 select SYS_FSL_ERRATUM_A010315
7
8config ARCH_LS1043A
York Sun4a444172016-10-04 14:31:47 -0700[diff] [blame]9 bool
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]10 select FSL_LSCH2
York Sun24aaa092016-10-04 18:03:08 -0700[diff] [blame]11 select SYS_FSL_DDR_BE
12 select SYS_FSL_DDR_VER_50
York Sun0a37cf82016-09-26 08:09:27 -0700[diff] [blame]13 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiang0ea36712016-09-29 12:42:44 +0800[diff] [blame]14 select SYS_FSL_ERRATUM_A010539
York Sun9533acf2016-09-26 08:09:26 -0700[diff] [blame]15
York Sunda28e582016-09-26 08:09:24 -0700[diff] [blame]16config ARCH_LS1046A
York Sun4a444172016-10-04 14:31:47 -0700[diff] [blame]17 bool
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]18 select FSL_LSCH2
York Sun24aaa092016-10-04 18:03:08 -0700[diff] [blame]19 select SYS_FSL_DDR_BE
20 select SYS_FSL_DDR4
21 select SYS_FSL_DDR_VER_50
Hou Zhiqiang0ea36712016-09-29 12:42:44 +0800[diff] [blame]22 select SYS_FSL_ERRATUM_A010539
York Sunf534b8f2016-10-04 18:01:34 -0700[diff] [blame]23 select SYS_FSL_SRDS_2
York Sun9533acf2016-09-26 08:09:26 -0700[diff] [blame]24
York Sun4a444172016-10-04 14:31:47 -0700[diff] [blame]25config ARCH_LS2080A
26 bool
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]27 select FSL_LSCH3
York Sun24aaa092016-10-04 18:03:08 -0700[diff] [blame]28 select SYS_FSL_DDR4
29 select SYS_FSL_DDR_LE
30 select SYS_FSL_DDR_VER_50
York Sunf534b8f2016-10-04 18:01:34 -0700[diff] [blame]31 select SYS_FSL_HAS_DP_DDR
32 select SYS_FSL_SRDS_2
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]33
34config FSL_LSCH2
35 bool
York Sunf534b8f2016-10-04 18:01:34 -0700[diff] [blame]36 select SYS_FSL_SRDS_1
37 select SYS_HAS_SERDES
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]38
39config FSL_LSCH3
40 bool
York Sunf534b8f2016-10-04 18:01:34 -0700[diff] [blame]41 select SYS_FSL_SRDS_1
42 select SYS_HAS_SERDES
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]43
44menu "Layerscape architecture"
45 depends on FSL_LSCH2 || FSL_LSCH3
York Sun4a444172016-10-04 14:31:47 -0700[diff] [blame]46
macro.wave.z@gmail.com2d16a1a2016-12-08 11:58:21 +0800[diff] [blame^]47menu "Layerscape PPA"
48config FSL_LS_PPA
49 bool "FSL Layerscape PPA firmware support"
50 depends on ARCH_LS1043A || ARCH_LS1046A
51 select FSL_PPA_ARMV8_PSCI
52 help
53 The FSL Primary Protected Application (PPA) is a software component
54 which is loaded during boot stage, and then remains resident in RAM
55 and runs in the TrustZone after boot.
56 Say y to enable it.
57
58config FSL_PPA_ARMV8_PSCI
59 bool "PSCI implementation in PPA firmware"
60 depends on FSL_LS_PPA
61 help
62 This config enables the ARMv8 PSCI implementation in PPA firmware.
63 This is a private PSCI implementation and different from those
64 implemented under the common ARMv8 PSCI framework.
65endmenu
66
York Sun9533acf2016-09-26 08:09:26 -0700[diff] [blame]67config SYS_FSL_MMDC
York Sun4a444172016-10-04 14:31:47 -0700[diff] [blame]68 bool
York Sun0a37cf82016-09-26 08:09:27 -0700[diff] [blame]69
70config SYS_FSL_ERRATUM_A010315
71 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiang0ea36712016-09-29 12:42:44 +0800[diff] [blame]72
73config SYS_FSL_ERRATUM_A010539
74 bool "Workaround for PIN MUX erratum A010539"
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]75
York Sunb4b60d02016-10-04 14:45:01 -0700[diff] [blame]76config MAX_CPUS
77 int "Maximum number of CPUs permitted for Layerscape"
78 default 4 if ARCH_LS1043A
79 default 4 if ARCH_LS1046A
80 default 16 if ARCH_LS2080A
81 default 1
82 help
83 Set this number to the maximum number of possible CPUs in the SoC.
84 SoCs may have multiple clusters with each cluster may have multiple
85 ports. If some ports are reserved but higher ports are used for
86 cores, count the reserved ports. This will allocate enough memory
87 in spin table to properly handle all cores.
88
York Sunfd638102016-10-04 14:46:50 -0700[diff] [blame]89config NUM_DDR_CONTROLLERS
90 int "Maximum DDR controllers"
91 default 3 if ARCH_LS2080A
92 default 1
93
York Sun01f65d92016-12-02 09:32:35 -0800[diff] [blame]94config SECURE_BOOT
95 bool
96 help
97 Enable Freescale Secure Boot feature
98
Yuan Yaodd2ad2f2016-12-01 10:13:52 +0800[diff] [blame]99config QSPI_AHB_INIT
100 bool "Init the QSPI AHB bus"
101 help
102 The default setting for QSPI AHB bus just support 3bytes addressing.
103 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
104 bus for those flashes to support the full QSPI flash size.
105
York Sun25af7dc2016-10-04 14:45:54 -0700[diff] [blame]106config SYS_FSL_IFC_BANK_COUNT
107 int "Maximum banks of Integrated flash controller"
108 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
109 default 4 if ARCH_LS1043A
110 default 4 if ARCH_LS1046A
111 default 8 if ARCH_LS2080A
112
York Sunfd638102016-10-04 14:46:50 -0700[diff] [blame]113config SYS_FSL_HAS_DP_DDR
114 bool
115
York Sunf534b8f2016-10-04 18:01:34 -0700[diff] [blame]116config SYS_FSL_SRDS_1
117 bool
118
119config SYS_FSL_SRDS_2
120 bool
121
122config SYS_HAS_SERDES
123 bool
124
York Sun24aaa092016-10-04 18:03:08 -0700[diff] [blame]125config SYS_FSL_DDR
126 bool "Freescale DDR driver"
127 help
128 Select Freescale General DDR driver, shared between most Freescale
129 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
130 based Layerscape SoCs (such as ls2080a).
131
132config SYS_FSL_DDR_BE
133 bool
134 help
135 Access DDR registers in big-endian.
136
137config SYS_FSL_DDR_LE
138 bool
139 help
140 Access DDR registers in little-endian.
141
142config SYS_FSL_DDR_VER
143 int
144 default 50 if SYS_FSL_DDR_VER_50
145
146config SYS_FSL_DDR_VER_50
147 bool
148
149config SYS_FSL_DDRC_ARM_GEN3
150 bool
151
152config SYS_FSL_DDRC_GEN4
153 bool
154
155config SYS_FSL_DDR3
156 bool "Freescale DDR3 controller"
157 depends on !SYS_FSL_DDR4
158 select SYS_FSL_DDR
159 select SYS_FSL_DDRC_ARM_GEN3
160 help
161 Enable Freescale DDR3 controller on ARM-based SoCs.
162
163config SYS_FSL_DDR4
164 bool "Freescale DDR4 controller"
165 select SYS_FSL_DDR
166 select SYS_FSL_DDRC_GEN4
167 help
168 Enable Freescale DDR4 controller.
169
York Sunfb2bf8c2016-10-04 14:31:48 -0700[diff] [blame]170endmenu