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gerrit.cesnet.cz / github / trini / u-boot / 2cf36ae7cf897b2a942db98e9e826539961fb55d / . / arch / arm / include / asm / arch-mx31 / mx31-regs.h
blob: 37337f2877a32446491e422ceaa71e9d651a3c7e [file] [log] [blame]
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]1/*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_MX31_REGS_H
25#define __ASM_ARCH_MX31_REGS_H
26
Magnus Liljac816dcb2009-11-11 20:18:42 +0100[diff] [blame]27#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28#include <asm/types.h>
29
30/* Clock control module registers */
31struct clock_control_regs {
32 u32 ccmr;
33 u32 pdr0;
34 u32 pdr1;
35 u32 rcsr;
36 u32 mpctl;
37 u32 upctl;
38 u32 spctl;
39 u32 cosr;
40 u32 cgr0;
41 u32 cgr1;
42 u32 cgr2;
43 u32 wimr0;
44 u32 ldc;
45 u32 dcvr0;
46 u32 dcvr1;
47 u32 dcvr2;
48 u32 dcvr3;
49 u32 ltr0;
50 u32 ltr1;
51 u32 ltr2;
52 u32 ltr3;
53 u32 ltbr0;
54 u32 ltbr1;
55 u32 pmcr0;
56 u32 pmcr1;
57 u32 pdr2;
58};
59
Stefano Babicc4ea1422010-07-06 17:05:06 +0200[diff] [blame]60/* GPIO Registers */
61struct gpio_regs {
62 u32 gpio_dr;
63 u32 gpio_dir;
64 u32 gpio_psr;
65};
66
Stefano Babicac87c172011-01-19 22:46:33 +0000[diff] [blame]67struct cspi_regs {
68 u32 rxdata;
69 u32 txdata;
70 u32 ctrl;
71 u32 intr;
72 u32 dma;
73 u32 stat;
74 u32 period;
75 u32 test;
76};
77
Stefano Babic2cf36ae2011-02-02 00:49:36 +0000[diff] [blame^]78/* Watchdog Timer (WDOG) registers */
79#define WDOG_ENABLE (1 << 2)
80#define WDOG_WT_SHIFT 8
81struct wdog_regs {
82 u16 wcr; /* Control */
83 u16 wsr; /* Service */
84 u16 wrsr; /* Reset Status */
85};
86
87
Stefano Babicf76888c2010-10-06 08:59:26 +0200[diff] [blame]88#define IOMUX_PADNUM_MASK 0x1ff
89#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
90
91/*
92 * various IOMUX pad functions
93 */
94enum iomux_pad_config {
95 PAD_CTL_NOLOOPBACK = 0x0 << 9,
96 PAD_CTL_LOOPBACK = 0x1 << 9,
97 PAD_CTL_PKE_NONE = 0x0 << 8,
98 PAD_CTL_PKE_ENABLE = 0x1 << 8,
99 PAD_CTL_PUE_KEEPER = 0x0 << 7,
100 PAD_CTL_PUE_PUD = 0x1 << 7,
101 PAD_CTL_100K_PD = 0x0 << 5,
102 PAD_CTL_100K_PU = 0x1 << 5,
103 PAD_CTL_47K_PU = 0x2 << 5,
104 PAD_CTL_22K_PU = 0x3 << 5,
105 PAD_CTL_HYS_CMOS = 0x0 << 4,
106 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
107 PAD_CTL_ODE_CMOS = 0x0 << 3,
108 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
109 PAD_CTL_DRV_NORMAL = 0x0 << 1,
110 PAD_CTL_DRV_HIGH = 0x1 << 1,
111 PAD_CTL_DRV_MAX = 0x2 << 1,
112 PAD_CTL_SRE_SLOW = 0x0 << 0,
113 PAD_CTL_SRE_FAST = 0x1 << 0
114};
115
116/*
117 * This enumeration is constructed based on the Section
118 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
119 * value is constructed based on the rules described above.
120 */
121
122enum iomux_pins {
123 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
124 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
125 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
126 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
127 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
128 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
129 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
130 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
131 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
132 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
133 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
134 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
135 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
136 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
137 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
138 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
139 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
140 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
141 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
142 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
143 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
144 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
145 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
146 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
147 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
148 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
149 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
150 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
151 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
152 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
153 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
154 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
155 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
156 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
157 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
158 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
159 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
160 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
161 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
162 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
163 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
164 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
165 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
166 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
167 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
168 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
169 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
170 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
171 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
172 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
173 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
174 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
175 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
176 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
177 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
178 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
179 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
180 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
181 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
182 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
183 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
184 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
185 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
186 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
187 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
188 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
189 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
190 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
191 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
192 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
193 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
194 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
195 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
196 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
197 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
198 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
199 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
200 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
201 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
202 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
203 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
204 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
205 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
206 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
207 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
208 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
209 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
210 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
211 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
212 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
213 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
214 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
215 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
216 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
217 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
218 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
219 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
220 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
221 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
222 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
223 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
224 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
225 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
226 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
227 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
228 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
229 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
230 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
231 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
232 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
233 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
234 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
235 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
236 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
237 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
238 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
239 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
240 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
241 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
242 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
243 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
244 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
245 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
246 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
247 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
248 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
249 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
250 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
251 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
252 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
253 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
254 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
255 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
256 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
257 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
258 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
259 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
260 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
261 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
262 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
263 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
264 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
265 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
266 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
267 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
268 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
269 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
270 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
271 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
272 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
273 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
274 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
275 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
276 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
277 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
278 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
279 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
280 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
281 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
282 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
283 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
284 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
285 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
286 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
287 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
288 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
289 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
290 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
291 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
292 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
293 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
294 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
295 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
296 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
297 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
298 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
299 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
300 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
301 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
302 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
303 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
304 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
305 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
306 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
307 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
308 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
309 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
310 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
311 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
312 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
313 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
314 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
315 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
316 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
317 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
318 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
319 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
320 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
321 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
322 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
323 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
324 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
325 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
326 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
327 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
328 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
329 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
330 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
331 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
332 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
333 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
334 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
335 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
336 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
337 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
338 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
339 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
340 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
341 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
342 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
343 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
344 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
345 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
346 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
347 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
348 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
349 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
350 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
351 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
352 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
353 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
354 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
355 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
356 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
357 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
358 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
359 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
360 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
361 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
362 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
363 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
364 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
365 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
366 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
367 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
368 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
369 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
370 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
371 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
372 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
373 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
374 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
375 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
376 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
377 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
378 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
379 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
380 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
381 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
382 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
383 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
384 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
385 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
386 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
387 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
388 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
389 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
390 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
391 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
392 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
393 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
394 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
395 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
396 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
397 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
398 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
399 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
400 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
401 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
402 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
403 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
404 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
405 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
406 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
407 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
408 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
409 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
410 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
411 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
412 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
413 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
414 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
415 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
416 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
417 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
418 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
419 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
420 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
421 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
422 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
423 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
424 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
425 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
426 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
427 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
428 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
429 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
430 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
431 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
432 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
433 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
434 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
435 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
436 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
437 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
438 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
439 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
440 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
441 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
442 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
443 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
444 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
445 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
446 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
447 MX31_PIN_PWMO = IOMUX_PIN(9, 324),
448 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
449 MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
450 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
451};
Stefano Babicc4ea1422010-07-06 17:05:06 +0200[diff] [blame]452
Magnus Liljac816dcb2009-11-11 20:18:42 +0100[diff] [blame]453/* Bit definitions for RCSR register in CCM */
454#define CCM_RCSR_NF16B (1 << 31)
455#define CCM_RCSR_NFMS (1 << 30)
456
457#endif
458
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]459#define __REG(x) (*((volatile u32 *)(x)))
460#define __REG16(x) (*((volatile u16 *)(x)))
461#define __REG8(x) (*((volatile u8 *)(x)))
462
463#define CCM_BASE 0x53f80000
464#define CCM_CCMR (CCM_BASE + 0x00)
465#define CCM_PDR0 (CCM_BASE + 0x04)
466#define CCM_PDR1 (CCM_BASE + 0x08)
467#define CCM_RCSR (CCM_BASE + 0x0c)
468#define CCM_MPCTL (CCM_BASE + 0x10)
Maxim Artamonov68553362008-12-03 05:38:17 +0300[diff] [blame]469#define CCM_UPCTL (CCM_BASE + 0x14)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]470#define CCM_SPCTL (CCM_BASE + 0x18)
471#define CCM_COSR (CCM_BASE + 0x1C)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200[diff] [blame]472#define CCM_CGR0 (CCM_BASE + 0x20)
473#define CCM_CGR1 (CCM_BASE + 0x24)
474#define CCM_CGR2 (CCM_BASE + 0x28)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]475
476#define CCMR_MDS (1 << 7)
477#define CCMR_SBYCS (1 << 4)
478#define CCMR_MPE (1 << 3)
479#define CCMR_PRCS_MASK (3 << 1)
480#define CCMR_FPM (1 << 1)
481#define CCMR_CKIH (2 << 1)
482
483#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
484#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
485#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
486#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
487#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
488#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
489#define PDR0_MCU_PODF(x) ((x) & 0x7)
490
491#define PLL_PD(x) (((x) & 0xf) << 26)
492#define PLL_MFD(x) (((x) & 0x3ff) << 16)
493#define PLL_MFI(x) (((x) & 0xf) << 10)
494#define PLL_MFN(x) (((x) & 0x3ff) << 0)
495
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200[diff] [blame]496#define WEIM_ESDCTL0 0xB8001000
497#define WEIM_ESDCFG0 0xB8001004
498#define WEIM_ESDCTL1 0xB8001008
499#define WEIM_ESDCFG1 0xB800100C
500#define WEIM_ESDMISC 0xB8001010
501
502#define ESDCTL_SDE (1 << 31)
503#define ESDCTL_CMD_RW (0 << 28)
504#define ESDCTL_CMD_PRECHARGE (1 << 28)
505#define ESDCTL_CMD_AUTOREFRESH (2 << 28)
506#define ESDCTL_CMD_LOADMODEREG (3 << 28)
507#define ESDCTL_CMD_MANUALREFRESH (4 << 28)
508#define ESDCTL_ROW_13 (2 << 24)
509#define ESDCTL_ROW(x) ((x) << 24)
510#define ESDCTL_COL_9 (1 << 20)
511#define ESDCTL_COL(x) ((x) << 20)
512#define ESDCTL_DSIZ(x) ((x) << 16)
513#define ESDCTL_SREFR(x) ((x) << 13)
514#define ESDCTL_PWDT(x) ((x) << 10)
515#define ESDCTL_FP(x) ((x) << 8)
516#define ESDCTL_BL(x) ((x) << 7)
517#define ESDCTL_PRCT(x) ((x) << 0)
518
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]519#define WEIM_BASE 0xb8002000
520#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
521#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
522#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
523
524#define IOMUXC_BASE 0x43FAC000
525#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
526#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
527#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
528
529#define IPU_BASE 0x53fc0000
530#define IPU_CONF IPU_BASE
531
532#define IPU_CONF_PXL_ENDIAN (1<<8)
533#define IPU_CONF_DU_EN (1<<7)
534#define IPU_CONF_DI_EN (1<<6)
535#define IPU_CONF_ADC_EN (1<<5)
536#define IPU_CONF_SDC_EN (1<<4)
537#define IPU_CONF_PF_EN (1<<3)
538#define IPU_CONF_ROT_EN (1<<2)
539#define IPU_CONF_IC_EN (1<<1)
540#define IPU_CONF_SCI_EN (1<<0)
541
Magnus Lilja8449f282009-07-01 01:07:55 +0200[diff] [blame]542#define ARM_PPMRR 0x40000015
543
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]544#define WDOG_BASE 0x53FDC000
545
546/*
Ilya Yanok54dc5172009-02-08 00:59:43 +0300[diff] [blame]547 * GPIO
548 */
Stefano Babicc4ea1422010-07-06 17:05:06 +0200[diff] [blame]549#define GPIO1_BASE_ADDR 0x53FCC000
550#define GPIO2_BASE_ADDR 0x53FD0000
551#define GPIO3_BASE_ADDR 0x53FA4000
Ilya Yanok54dc5172009-02-08 00:59:43 +0300[diff] [blame]552#define GPIO_DR 0x00000000 /* data register */
553#define GPIO_GDIR 0x00000004 /* direction register */
554#define GPIO_PSR 0x00000008 /* pad status register */
555
556/*
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]557 * Signal Multiplexing (IOMUX)
558 */
559
560/* bits in the SW_MUX_CTL registers */
561#define MUX_CTL_OUT_GPIO_DR (0 << 4)
562#define MUX_CTL_OUT_FUNC (1 << 4)
563#define MUX_CTL_OUT_ALT1 (2 << 4)
564#define MUX_CTL_OUT_ALT2 (3 << 4)
565#define MUX_CTL_OUT_ALT3 (4 << 4)
566#define MUX_CTL_OUT_ALT4 (5 << 4)
567#define MUX_CTL_OUT_ALT5 (6 << 4)
568#define MUX_CTL_OUT_ALT6 (7 << 4)
569#define MUX_CTL_IN_NONE (0 << 0)
570#define MUX_CTL_IN_GPIO (1 << 0)
571#define MUX_CTL_IN_FUNC (2 << 0)
572#define MUX_CTL_IN_ALT1 (4 << 0)
573#define MUX_CTL_IN_ALT2 (8 << 0)
574
575#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
576#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
577#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
578#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
579
580/* Register offsets based on IOMUXC_BASE */
581/* 0x00 .. 0x7b */
Stefano Babicf76888c2010-10-06 08:59:26 +0200[diff] [blame]582#define MUX_CTL_USBH2_DATA1 0x40
583#define MUX_CTL_USBH2_DIR 0x44
584#define MUX_CTL_USBH2_STP 0x45
585#define MUX_CTL_USBH2_NXT 0x46
586#define MUX_CTL_USBH2_DATA0 0x47
587#define MUX_CTL_USBH2_CLK 0x4B
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]588#define MUX_CTL_RTS1 0x7c
589#define MUX_CTL_CTS1 0x7d
590#define MUX_CTL_DTR_DCE1 0x7e
591#define MUX_CTL_DSR_DCE1 0x7f
592#define MUX_CTL_CSPI2_SCLK 0x80
593#define MUX_CTL_CSPI2_SPI_RDY 0x81
594#define MUX_CTL_RXD1 0x82
595#define MUX_CTL_TXD1 0x83
596#define MUX_CTL_CSPI2_MISO 0x84
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200[diff] [blame]597#define MUX_CTL_CSPI2_SS0 0x85
598#define MUX_CTL_CSPI2_SS1 0x86
599#define MUX_CTL_CSPI2_SS2 0x87
Guennadi Liakhovetskia2bb7102009-02-24 10:44:02 +0100[diff] [blame]600#define MUX_CTL_CSPI1_SS2 0x88
601#define MUX_CTL_CSPI1_SCLK 0x89
602#define MUX_CTL_CSPI1_SPI_RDY 0x8a
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]603#define MUX_CTL_CSPI2_MOSI 0x8b
Guennadi Liakhovetskia2bb7102009-02-24 10:44:02 +0100[diff] [blame]604#define MUX_CTL_CSPI1_MOSI 0x8c
605#define MUX_CTL_CSPI1_MISO 0x8d
606#define MUX_CTL_CSPI1_SS0 0x8e
607#define MUX_CTL_CSPI1_SS1 0x8f
Stefano Babic70e23262010-10-01 12:34:34 +0200[diff] [blame]608#define MUX_CTL_STXD6 0x90
609#define MUX_CTL_SRXD6 0x91
610#define MUX_CTL_SCK6 0x92
611#define MUX_CTL_SFS6 0x93
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]612
Stefano Babicf76888c2010-10-06 08:59:26 +0200[diff] [blame]613#define MUX_CTL_STXD3 0x9C
614#define MUX_CTL_SRXD3 0x9D
615#define MUX_CTL_SCK3 0x9E
616#define MUX_CTL_SFS3 0x9F
617
Stefano Babicefb95912010-03-29 15:56:10 +0200[diff] [blame]618#define MUX_CTL_NFC_WP 0xD0
619#define MUX_CTL_NFC_CE 0xD1
620#define MUX_CTL_NFC_RB 0xD2
621#define MUX_CTL_NFC_WE 0xD4
622#define MUX_CTL_NFC_RE 0xD5
623#define MUX_CTL_NFC_ALE 0xD6
624#define MUX_CTL_NFC_CLE 0xD7
625
626
Stefano Babic70e23262010-10-01 12:34:34 +0200[diff] [blame]627#define MUX_CTL_CAPTURE 0x150
628#define MUX_CTL_COMPARE 0x151
629
Magnus Lilja5276a352008-08-03 21:44:10 +0200[diff] [blame]630/*
631 * Helper macros for the MUX_[contact name]__[pin function] macros
632 */
633#define IOMUX_MODE_POS 9
634#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
635
636/*
637 * These macros can be used in mx31_gpio_mux() and have the form
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]638 * MUX_[contact name]__[pin function]
639 */
Magnus Lilja5276a352008-08-03 21:44:10 +0200[diff] [blame]640#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
641#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
642#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
643#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]644
Magnus Lilja5276a352008-08-03 21:44:10 +0200[diff] [blame]645#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
646#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
647#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
648#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
649#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
650#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
651 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
652#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
653
Guennadi Liakhovetskia2bb7102009-02-24 10:44:02 +0100[diff] [blame]654#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
655#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
656#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
657#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
658#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
659#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
660 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
661#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
662
Magnus Lilja5276a352008-08-03 21:44:10 +0200[diff] [blame]663#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
664#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]665
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200[diff] [blame]666/* PAD control registers for SDR/DDR */
667#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
668#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
669#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
670#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
671#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
672#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
673#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
674#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
675#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
676#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
677#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
678#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
679#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
680#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
681#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
682#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
683#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
684#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
685#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
686#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
687#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
688#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
689#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
690#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
691#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
692#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
693#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
694#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
695#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
696
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200[diff] [blame]697/*
698 * Memory regions and CS
699 */
700#define IPU_MEM_BASE 0x70000000
701#define CSD0_BASE 0x80000000
702#define CSD1_BASE 0x90000000
703#define CS0_BASE 0xA0000000
704#define CS1_BASE 0xA8000000
705#define CS2_BASE 0xB0000000
706#define CS3_BASE 0xB2000000
707#define CS4_BASE 0xB4000000
708#define CS4_PSRAM_BASE 0xB5000000
709#define CS5_BASE 0xB6000000
710#define PCMCIA_MEM_BASE 0xC0000000
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]711
Magnus Lilja40c642b2009-06-13 20:50:01 +0200[diff] [blame]712/*
713 * NAND controller
714 */
715#define NFC_BASE_ADDR 0xB8000000
716
Stefano Babiceab40f82010-03-31 10:27:47 +0200[diff] [blame]717/*
718 * Internal RAM (16KB)
719 */
720#define IRAM_BASE_ADDR 0x1FFFC000
721#define IRAM_SIZE (16 * 1024)
722
Stefano Babicf76888c2010-10-06 08:59:26 +0200[diff] [blame]723#define MX31_AIPS1_BASE_ADDR 0x43f00000
724#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
725
726/* USB portsc */
727/* values for portsc field */
728#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
729#define MXC_EHCI_FORCE_FS (1 << 24)
730#define MXC_EHCI_UTMI_8BIT (0 << 28)
731#define MXC_EHCI_UTMI_16BIT (1 << 28)
732#define MXC_EHCI_SERIAL (1 << 29)
733#define MXC_EHCI_MODE_UTMI (0 << 30)
734#define MXC_EHCI_MODE_PHILIPS (1 << 30)
735#define MXC_EHCI_MODE_ULPI (2 << 30)
736#define MXC_EHCI_MODE_SERIAL (3 << 30)
737
738/* values for flags field */
739#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
740#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
741#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
742#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
743#define MXC_EHCI_INTERFACE_MASK (0xf)
744
745#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
746#define MXC_EHCI_TTL_ENABLED (1 << 6)
747
748#define MXC_EHCI_INTERNAL_PHY (1 << 7)
749#define MXC_EHCI_IPPUE_DOWN (1 << 8)
750#define MXC_EHCI_IPPUE_UP (1 << 9)
751
Sascha Hauer9b56f4f2008-03-26 20:40:42 +0100[diff] [blame]752#endif /* __ASM_ARCH_MX31_REGS_H */