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gerrit.cesnet.cz / github / trini / u-boot / 2ce4eaf4c89e371aeb69392b68dbb2f705c28144 / . / arch / arm / cpu / armv7 / keystone / clock-k2hk.c
blob: 1591960795d85c65abb0ed2672b999e82b598c95 [file] [log] [blame]
Khoronzhuk, Ivan8dfc15f2014-07-09 23:44:47 +0300[diff] [blame]1/*
2 * Keystone2: get clk rate for K2HK
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/clock_defs.h>
13
14const struct keystone_pll_regs keystone_pll_regs[] = {
15 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
16 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
17 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
18 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
19 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
20};
21
Vitaly Andrianov61f66fd2014-07-25 22:23:19 +0300[diff] [blame]22int dev_speeds[] = {
23 SPD800,
24 SPD1000,
25 SPD1200,
26 SPD800,
27 SPD800,
28 SPD800,
29 SPD800,
30 SPD800,
31 SPD1200,
32 SPD1000,
33 SPD800,
34 SPD800,
35 SPD800,
36};
37
38int arm_speeds[] = {
39 SPD800,
40 SPD1000,
41 SPD1200,
42 SPD1350,
43 SPD1400,
44 SPD800,
45 SPD1400,
46 SPD1350,
47 SPD1200,
48 SPD1000,
49 SPD800,
50 SPD800,
51 SPD800,
52};
53
Khoronzhuk, Ivan8dfc15f2014-07-09 23:44:47 +0300[diff] [blame]54/**
55 * pll_freq_get - get pll frequency
56 * Fout = Fref * NF(mult) / NR(prediv) / OD
57 * @pll: pll identifier
58 */
59static unsigned long pll_freq_get(int pll)
60{
61 unsigned long mult = 1, prediv = 1, output_div = 2;
62 unsigned long ret;
63 u32 tmp, reg;
64
65 if (pll == CORE_PLL) {
66 ret = external_clk[sys_clk];
67 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
68 /* PLL mode */
69 tmp = __raw_readl(KS2_MAINPLLCTL0);
70 prediv = (tmp & PLL_DIV_MASK) + 1;
71 mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
72 (pllctl_reg_read(pll, mult) &
73 PLLM_MULT_LO_MASK)) + 1;
74 output_div = ((pllctl_reg_read(pll, secctl) >>
75 PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
76
77 ret = ret / prediv / output_div * mult;
78 }
79 } else {
80 switch (pll) {
81 case PASS_PLL:
82 ret = external_clk[pa_clk];
83 reg = KS2_PASSPLLCTL0;
84 break;
85 case TETRIS_PLL:
86 ret = external_clk[tetris_clk];
87 reg = KS2_ARMPLLCTL0;
88 break;
89 case DDR3A_PLL:
90 ret = external_clk[ddr3a_clk];
91 reg = KS2_DDR3APLLCTL0;
92 break;
93 case DDR3B_PLL:
94 ret = external_clk[ddr3b_clk];
95 reg = KS2_DDR3BPLLCTL0;
96 break;
97 default:
98 return 0;
99 }
100
101 tmp = __raw_readl(reg);
102
103 if (!(tmp & PLLCTL_BYPASS)) {
104 /* Bypass disabled */
105 prediv = (tmp & PLL_DIV_MASK) + 1;
106 mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
107 output_div = ((tmp >> PLL_CLKOD_SHIFT) &
108 PLL_CLKOD_MASK) + 1;
109 ret = ((ret / prediv) * mult) / output_div;
110 }
111 }
112
113 return ret;
114}
115
116unsigned long clk_get_rate(unsigned int clk)
117{
118 switch (clk) {
119 case core_pll_clk: return pll_freq_get(CORE_PLL);
120 case pass_pll_clk: return pll_freq_get(PASS_PLL);
121 case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
122 case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
123 case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
124 case sys_clk0_1_clk:
125 case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
126 case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
127 case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
128 case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
129 case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
130 case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
131 case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
132 case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
133 case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
134 case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
135 case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
136 case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
137 case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
138 case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
139 case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
140 default:
141 break;
142 }
143
144 return 0;
145}