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gerrit.cesnet.cz / github / trini / u-boot / 2cc393f32fd9ffcf47f4877e8d1345a7981a0d02 / . / configs / tinker-rk3288_defconfig
blob: 83c34508391a04ac4d09bf068845b145efe0a02c [file] [log] [blame]
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Kever Yangd79036c2019-07-01 11:49:13 +0800[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x01000000
Tom Rini665c35a2019-09-23 11:47:37 -0400[diff] [blame]4CONFIG_SPL_GPIO_SUPPORT=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]5CONFIG_ROCKCHIP_RK3288=y
Eddie Cai6f279762017-01-18 11:03:54 +0800[diff] [blame]6CONFIG_TARGET_TINKER_RK3288=y
Tom Rinia09fea12019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_OFFSET=0x3F8000
Tom Rini59e5d1e2019-11-11 20:04:24 -0500[diff] [blame]8CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinid168bcb2019-04-29 15:54:04 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
Simon Glassb51882d2019-09-25 08:56:28 -0600[diff] [blame]10CONFIG_SPL_SIZE_LIMIT=0x4b000
Tom Rini358b6a22018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_DEBUG_UART_BASE=0xff690000
12CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rinifb82fe32017-06-19 09:47:40 -0400[diff] [blame]13CONFIG_DEBUG_UART=y
Tom Rini48f62322017-08-25 17:50:27 -0400[diff] [blame]14# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass37304aa2019-07-20 20:51:14 -0600[diff] [blame]15CONFIG_USE_PREBOOT=y
Simon Glass98af8792016-10-17 20:12:35 -0600[diff] [blame]16CONFIG_SILENT_CONSOLE=y
Simon Glassef26d602016-10-17 20:12:37 -0600[diff] [blame]17CONFIG_CONSOLE_MUX=y
Klaus Gogera2a50532018-05-25 23:45:05 +0200[diff] [blame]18CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
Simon Glassef26d602016-10-17 20:12:37 -0600[diff] [blame]19# CONFIG_DISPLAY_CPUINFO is not set
Mario Six78eba692018-03-28 14:38:17 +0200[diff] [blame]20CONFIG_DISPLAY_BOARDINFO_LATE=y
Jagan Teki4bd143b2019-09-17 11:40:41 +0530[diff] [blame]21CONFIG_SPL_STACK_R=y
22CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rini665c35a2019-09-23 11:47:37 -0400[diff] [blame]23CONFIG_SPL_I2C_SUPPORT=y
24CONFIG_SPL_POWER_SUPPORT=y
Tom Rini88663122017-08-14 19:58:53 -0400[diff] [blame]25CONFIG_CMD_GPIO=y
Patrick Delaunayb331cd62017-01-27 11:00:42 +0100[diff] [blame]26CONFIG_CMD_GPT=y
Tom Rini88663122017-08-14 19:58:53 -0400[diff] [blame]27CONFIG_CMD_I2C=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]28CONFIG_CMD_MMC=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]29CONFIG_CMD_SPI=y
Eddie Caic00d1652017-03-07 12:47:07 +0800[diff] [blame]30CONFIG_CMD_USB=y
Urja Rannikkoa186e8a2019-05-13 13:51:04 +0000[diff] [blame]31CONFIG_CMD_USB_MASS_STORAGE=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]32# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]33CONFIG_CMD_CACHE=y
34CONFIG_CMD_TIME=y
35CONFIG_CMD_PMIC=y
36CONFIG_CMD_REGULATOR=y
Patrick Delaunayb0cf7332017-01-27 11:00:37 +0100[diff] [blame]37# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunaybd42a942017-01-27 11:00:41 +0100[diff] [blame]38# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunayb331cd62017-01-27 11:00:42 +0100[diff] [blame]39CONFIG_SPL_PARTITION_UUIDS=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]40CONFIG_SPL_OF_CONTROL=y
Tom Rini8c5cad02018-09-03 15:26:12 -0400[diff] [blame]41CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
Kever Yangd79036c2019-07-01 11:49:13 +0800[diff] [blame]42CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5dc4dfd2017-08-28 07:16:32 -0400[diff] [blame]43CONFIG_ENV_IS_IN_MMC=y
Tom Rini8d8ee472019-11-12 22:46:36 -0500[diff] [blame]44CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]45CONFIG_REGMAP=y
46CONFIG_SPL_REGMAP=y
47CONFIG_SYSCON=y
48CONFIG_SPL_SYSCON=y
49# CONFIG_SPL_SIMPLE_BUS is not set
50CONFIG_CLK=y
51CONFIG_SPL_CLK=y
Alex Kiernan65c96752018-05-29 15:30:55 +0000[diff] [blame]52CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]53CONFIG_ROCKCHIP_GPIO=y
54CONFIG_SYS_I2C_ROCKCHIP=y
Jonas Karlmanecc3bd72017-04-22 08:57:54 +0000[diff] [blame]55CONFIG_MISC=y
56CONFIG_I2C_EEPROM=y
Masahiro Yamada55ed3b42017-01-10 13:32:04 +0900[diff] [blame]57CONFIG_MMC_DW=y
Masahiro Yamadafed44082017-01-10 13:32:03 +0900[diff] [blame]58CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal888f1842019-10-03 19:50:05 +0200[diff] [blame]59CONFIG_MTD=y
Patrick Delaunay14453fb2019-02-27 15:20:36 +0100[diff] [blame]60CONFIG_SF_DEFAULT_SPEED=20000000
Jacob Chen5c0206c2017-02-23 14:20:17 +0800[diff] [blame]61CONFIG_DM_ETH=y
Jacob Chen5c0206c2017-02-23 14:20:17 +0800[diff] [blame]62CONFIG_ETH_DESIGNWARE=y
63CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]64CONFIG_PINCTRL=y
65CONFIG_SPL_PINCTRL=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]66CONFIG_DM_PMIC=y
Jacob Chen453c5a92017-05-02 14:54:52 +0800[diff] [blame]67CONFIG_PMIC_RK8XX=y
Michael Trimarchif810ea62019-09-17 11:40:42 +0530[diff] [blame]68CONFIG_SPL_DM_REGULATOR=y
Tom Rini665c35a2019-09-23 11:47:37 -0400[diff] [blame]69CONFIG_DM_REGULATOR_FIXED=y
Michael Trimarchif810ea62019-09-17 11:40:42 +0530[diff] [blame]70CONFIG_SPL_DM_REGULATOR_FIXED=y
Tom Rini665c35a2019-09-23 11:47:37 -0400[diff] [blame]71CONFIG_REGULATOR_RK8XX=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]72CONFIG_PWM_ROCKCHIP=y
73CONFIG_RAM=y
74CONFIG_SPL_RAM=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]75CONFIG_DEBUG_UART_SHIFT=2
Tom Riniaca5cd22016-09-08 16:11:59 -0400[diff] [blame]76CONFIG_SYSRESET=y
Eddie Caic00d1652017-03-07 12:47:07 +0800[diff] [blame]77CONFIG_USB=y
Philipp Tomsich4ac72f52017-07-03 18:30:06 +0200[diff] [blame]78CONFIG_USB_DWC2=y
Adam Ford65748642018-01-02 10:39:52 -0600[diff] [blame]79CONFIG_ROCKCHIP_USB2_PHY=y
Tom Riniecad7052017-08-25 17:50:26 -0400[diff] [blame]80CONFIG_USB_GADGET=y
81CONFIG_USB_GADGET_DWC2_OTG=y
Chris Packhamae358442017-08-28 20:50:45 +1200[diff] [blame]82CONFIG_USB_HOST_ETHER=y
Chris Packhamf58ad982017-08-28 20:50:46 +1200[diff] [blame]83CONFIG_USB_ETHER_ASIX=y
84CONFIG_USB_ETHER_SMSC95XX=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]85CONFIG_CMD_DHRYSTONE=y
86CONFIG_ERRNO_STR=y