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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * Rick Bronson <rick@efn.org>
3 *
4 * Configuation settings for the AT91RM9200DK board.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/* ARM asynchronous clock */
wdenk8b07a112004-07-10 21:45:47 +000029#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
wdenkdc7c9a12003-03-26 06:55:25 +000032
wdenkd9df1f42004-03-15 09:00:01 +000033#define AT91_SLOW_CLOCK 32768 /* slow clock */
34
wdenka85f9f22005-04-06 13:52:31 +000035#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define USE_920T_MMU 1
40
wdenk8b07a112004-07-10 21:45:47 +000041#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenkdc7c9a12003-03-26 06:55:25 +000042#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk8b07a112004-07-10 21:45:47 +000043#define CONFIG_INITRD_TAG 1
wdenk2abbe072003-06-16 23:50:08 +000044
wdenk8aa1a2d2005-04-04 12:44:11 +000045#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkef2807c2005-03-31 23:44:33 +000046#define CFG_USE_MAIN_OSCILLATOR 1
47/* flash */
48#define MC_PUIA_VAL 0x00000000
49#define MC_PUP_VAL 0x00000000
50#define MC_PUER_VAL 0x00000000
51#define MC_ASR_VAL 0x00000000
52#define MC_AASR_VAL 0x00000000
53#define EBI_CFGR_VAL 0x00000000
54#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
55
56/* clocks */
57#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
58#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
59#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
60
61/* sdram */
62#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63#define PIOC_BSR_VAL 0x00000000
64#define PIOC_PDR_VAL 0xFFFF0000
65#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
66#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
67#define SDRAM 0x20000000 /* address of the SDRAM */
68#define SDRAM1 0x20000080 /* address of the SDRAM */
69#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
70#define SDRC_MR_VAL 0x00000002 /* Precharge All */
71#define SDRC_MR_VAL1 0x00000004 /* refresh */
72#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
wdenk8aa1a2d2005-04-04 12:44:11 +000075#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkdc7c9a12003-03-26 06:55:25 +000076/*
77 * Size of malloc() pool
78 */
79#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenka8c7c702003-12-06 19:49:23 +000080#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
81
wdenkdc7c9a12003-03-26 06:55:25 +000082#define CONFIG_BAUDRATE 115200
wdenka8c7c702003-12-06 19:49:23 +000083
wdenkdc7c9a12003-03-26 06:55:25 +000084/*
85 * Hardware drivers
86 */
87
wdenk9d5028c2004-11-21 00:06:33 +000088/* define one of these to choose the DBGU, USART0 or USART1 as console */
wdenk4734cb72004-09-21 23:33:32 +000089#define CONFIG_DBGU
wdenk9d5028c2004-11-21 00:06:33 +000090#undef CONFIG_USART0
wdenk4734cb72004-09-21 23:33:32 +000091#undef CONFIG_USART1
92
wdenkdc7c9a12003-03-26 06:55:25 +000093#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
94
95#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
96
wdenk8bde7f72003-06-27 21:31:46 +000097#define CONFIG_BOOTDELAY 3
wdenk8b07a112004-07-10 21:45:47 +000098/* #define CONFIG_ENV_OVERWRITE 1 */
wdenk2abbe072003-06-16 23:50:08 +000099
wdenk8bde7f72003-06-27 21:31:46 +0000100
Jon Loeliger0b361c92007-07-04 22:31:42 -0500101/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500102 * BOOTP options
103 */
104#define CONFIG_BOOTP_BOOTFILESIZE
105#define CONFIG_BOOTP_BOOTPATH
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108
109
110/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500111 * Command line configuration.
112 */
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_MII
116#define CONFIG_CMD_DHCP
117
118#undef CONFIG_CMD_BDI
119#undef CONFIG_CMD_IMI
120#undef CONFIG_CMD_AUTOSCRIPT
121#undef CONFIG_CMD_FPGA
122#undef CONFIG_CMD_MISC
123#undef CONFIG_CMD_LOADS
124
wdenkdc7c9a12003-03-26 06:55:25 +0000125
126#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
127#define SECTORSIZE 512
128
129#define ADDR_COLUMN 1
130#define ADDR_PAGE 2
131#define ADDR_COLUMN_PAGE 3
132
wdenk8b07a112004-07-10 21:45:47 +0000133#define NAND_ChipID_UNKNOWN 0x00
wdenkdc7c9a12003-03-26 06:55:25 +0000134#define NAND_MAX_FLOORS 1
135#define NAND_MAX_CHIPS 1
136
wdenk8b07a112004-07-10 21:45:47 +0000137#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
138#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
wdenkdc7c9a12003-03-26 06:55:25 +0000139
140#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
141#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
142
143#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
144
145#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
146#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
147#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
148#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
149/* the following are NOP's in our implementation */
150#define NAND_CTL_CLRALE(nandptr)
151#define NAND_CTL_SETALE(nandptr)
152#define NAND_CTL_CLRCLE(nandptr)
153#define NAND_CTL_SETCLE(nandptr)
154
155#define CONFIG_NR_DRAM_BANKS 1
156#define PHYS_SDRAM 0x20000000
157#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
158
wdenk8b07a112004-07-10 21:45:47 +0000159#define CFG_MEMTEST_START PHYS_SDRAM
160#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
wdenkdc7c9a12003-03-26 06:55:25 +0000161
162#define CONFIG_DRIVER_ETHER
wdenk8b07a112004-07-10 21:45:47 +0000163#define CONFIG_NET_RETRY_COUNT 20
wdenk074cff02004-02-24 00:16:43 +0000164#define CONFIG_AT91C_USE_RMII
wdenk2abbe072003-06-16 23:50:08 +0000165
Peter Pearsed4fc6012007-08-14 10:10:52 +0100166/* AC Characteristics */
167/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
168#define DATAFLASH_TCSS (0xC << 16)
169#define DATAFLASH_TCHS (0x1 << 24)
170
wdenk8b07a112004-07-10 21:45:47 +0000171#define CONFIG_HAS_DATAFLASH 1
172#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100173#define CFG_MAX_DATAFLASH_BANKS 2
174#define CFG_MAX_DATAFLASH_PAGES 16384
wdenk2abbe072003-06-16 23:50:08 +0000175#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
176#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
wdenkdc7c9a12003-03-26 06:55:25 +0000177
wdenk8b07a112004-07-10 21:45:47 +0000178#define PHYS_FLASH_1 0x10000000
179#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
180#define CFG_FLASH_BASE PHYS_FLASH_1
181#define CFG_MAX_FLASH_BANKS 1
182#define CFG_MAX_FLASH_SECT 256
183#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
184#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
wdenk5779d8d2003-12-06 23:55:10 +0000185
186#undef CFG_ENV_IS_IN_DATAFLASH
187
188#ifdef CFG_ENV_IS_IN_DATAFLASH
wdenk8b07a112004-07-10 21:45:47 +0000189#define CFG_ENV_OFFSET 0x20000
190#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
191#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
wdenk5779d8d2003-12-06 23:55:10 +0000192#else
wdenk8b07a112004-07-10 21:45:47 +0000193#define CFG_ENV_IS_IN_FLASH 1
wdenk8aa1a2d2005-04-04 12:44:11 +0000194#ifdef CONFIG_SKIP_LOWLEVEL_INIT
wdenk9d5028c2004-11-21 00:06:33 +0000195#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
wdenk8b07a112004-07-10 21:45:47 +0000196#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
Ladislav Michl481f28b2007-12-06 22:59:16 +0100197#else
198#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
199#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
wdenk8aa1a2d2005-04-04 12:44:11 +0000200#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenk400558b2005-04-02 23:52:25 +0000201#endif /* CFG_ENV_IS_IN_DATAFLASH */
wdenk5779d8d2003-12-06 23:55:10 +0000202
203
wdenk8b07a112004-07-10 21:45:47 +0000204#define CFG_LOAD_ADDR 0x21000000 /* default load address */
wdenkdc7c9a12003-03-26 06:55:25 +0000205
wdenk8aa1a2d2005-04-04 12:44:11 +0000206#ifdef CONFIG_SKIP_LOWLEVEL_INIT
wdenk2abbe072003-06-16 23:50:08 +0000207#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
wdenk8b07a112004-07-10 21:45:47 +0000208#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
209#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
Ladislav Michl481f28b2007-12-06 22:59:16 +0100210#else
211#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
212#define CFG_U_BOOT_BASE PHYS_FLASH_1
213#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
wdenk8aa1a2d2005-04-04 12:44:11 +0000214#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenk2abbe072003-06-16 23:50:08 +0000215
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100216#define CFG_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
wdenkdc7c9a12003-03-26 06:55:25 +0000217
wdenk8b07a112004-07-10 21:45:47 +0000218#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
219#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
220#define CFG_MAXARGS 16 /* max number of command args */
221#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000222
wdenk9455b7f2004-10-11 22:25:49 +0000223#define CFG_HZ 1000
224#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100225 /* AT91C_TC_TIMER_DIV1_CLOCK */
wdenkdc7c9a12003-03-26 06:55:25 +0000226
227#define CONFIG_STACKSIZE (32*1024) /* regular stack */
228
229#ifdef CONFIG_USE_IRQ
230#error CONFIG_USE_IRQ not supported
231#endif
232
233#endif