blob: 898fb5767e80272c4094ddb4f77b57b33e538906 [file] [log] [blame]
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +09001/*
2 * board/renesas/lager/lager.c
3 * This file is lager board support.
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#include <common.h>
12#include <malloc.h>
13#include <netdev.h>
14#include <asm/processor.h>
15#include <asm/mach-types.h>
16#include <asm/io.h>
17#include <asm/errno.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/gpio.h>
20#include <asm/arch/rmobile.h>
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090021#include <miiphy.h>
Nobuhiro Iwamatsub9986be2013-10-10 09:13:41 +090022#include <i2c.h>
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090023#include "qos.h"
24
25DECLARE_GLOBAL_DATA_PTR;
26
Nobuhiro Iwamatsu2c2c6ba2014-03-31 14:14:25 +090027#define CLK2MHZ(clk) (clk / 1000 / 1000)
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090028void s_init(void)
29{
Nobuhiro Iwamatsudc535e12014-03-27 16:18:19 +090030 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
31 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
Nobuhiro Iwamatsu2c2c6ba2014-03-31 14:14:25 +090032 u32 stc;
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090033
34 /* Watchdog init */
35 writel(0xA5A5A500, &rwdt->rwtcsra);
36 writel(0xA5A5A500, &swdt->swtcsra);
37
Nobuhiro Iwamatsu2c2c6ba2014-03-31 14:14:25 +090038 /* CPU frequency setting. Set to 1.4GHz */
39 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
40 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
41
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090042 /* QoS(Quality-of-Service) Init */
43 qos_init();
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090044}
45
46#define MSTPSR1 0xE6150038
47#define SMSTPCR1 0xE6150134
48#define TMU0_MSTP125 (1 << 25)
49
50#define MSTPSR7 0xE61501C4
51#define SMSTPCR7 0xE615014C
52#define SCIF0_MSTP721 (1 << 21)
53
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090054#define MSTPSR8 0xE61509A0
55#define SMSTPCR8 0xE6150990
56#define ETHER_MSTP813 (1 << 13)
57
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090058#define mstp_setbits(type, addr, saddr, set) \
59 out_##type((saddr), in_##type(addr) | (set))
60#define mstp_clrbits(type, addr, saddr, clear) \
61 out_##type((saddr), in_##type(addr) & ~(clear))
62#define mstp_setbits_le32(addr, saddr, set) \
63 mstp_setbits(le32, addr, saddr, set)
64#define mstp_clrbits_le32(addr, saddr, clear) \
65 mstp_clrbits(le32, addr, saddr, clear)
66
67int board_early_init_f(void)
68{
69 /* TMU0 */
70 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090071 /* SCIF0 */
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090072 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090073 /* ETHER */
74 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
75
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090076 return 0;
77}
78
Nobuhiro Iwamatsu16bf36f2013-10-11 15:00:37 +090079void arch_preboot_os(void)
80{
81 /* Disable TMU0 */
82 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
83}
84
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090085DECLARE_GLOBAL_DATA_PTR;
86int board_init(void)
87{
88 /* board id for linux */
89 gd->bd->bi_arch_number = MACH_TYPE_LAGER;
90 /* adress of boot parameters */
91 gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
92
93 /* Init PFC controller */
94 r8a7790_pinmux_init();
95
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090096 /* ETHER Enable */
97 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
98 gpio_request(GPIO_FN_ETH_RX_ER, NULL);
99 gpio_request(GPIO_FN_ETH_RXD0, NULL);
100 gpio_request(GPIO_FN_ETH_RXD1, NULL);
101 gpio_request(GPIO_FN_ETH_LINK, NULL);
102 gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
103 gpio_request(GPIO_FN_ETH_MDIO, NULL);
104 gpio_request(GPIO_FN_ETH_TXD1, NULL);
105 gpio_request(GPIO_FN_ETH_TX_EN, NULL);
106 gpio_request(GPIO_FN_ETH_MAGIC, NULL);
107 gpio_request(GPIO_FN_ETH_TXD0, NULL);
108 gpio_request(GPIO_FN_ETH_MDC, NULL);
109 gpio_request(GPIO_FN_IRQ0, NULL);
110
111 gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
112 gpio_direction_output(GPIO_GP_5_31, 0);
113 mdelay(20);
114 gpio_set_value(GPIO_GP_5_31, 1);
115 udelay(1);
116
117 return 0;
118}
119
120#define CXR24 0xEE7003C0 /* MAC address high register */
121#define CXR25 0xEE7003C8 /* MAC address low register */
122int board_eth_init(bd_t *bis)
123{
124 int ret = -ENODEV;
125
126#ifdef CONFIG_SH_ETHER
127 u32 val;
128 unsigned char enetaddr[6];
129
130 ret = sh_eth_initialize(bis);
131 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
132 return ret;
133
134 /* Set Mac address */
135 val = enetaddr[0] << 24 | enetaddr[1] << 16 |
136 enetaddr[2] << 8 | enetaddr[3];
137 writel(val, CXR24);
138
139 val = enetaddr[4] << 8 | enetaddr[5];
140 writel(val, CXR25);
141
142#endif
143
144 return ret;
145}
146
147/* lager has KSZ8041NL/RNL */
148#define PHY_CONTROL1 0x1E
149#define PHY_LED_MODE 0xC0000
150#define PHY_LED_MODE_ACK 0x4000
151int board_phy_config(struct phy_device *phydev)
152{
153 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
154 ret &= ~PHY_LED_MODE;
155 ret |= PHY_LED_MODE_ACK;
156 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
157
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +0900158 return 0;
159}
160
161int dram_init(void)
162{
163 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
164 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
165
166 return 0;
167}
168
169const struct rmobile_sysinfo sysinfo = {
170 CONFIG_RMOBILE_BOARD_STRING
171};
172
173void dram_init_banksize(void)
174{
175 gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
176 gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
177}
178
179int board_late_init(void)
180{
181 return 0;
182}
183
184void reset_cpu(ulong addr)
185{
Nobuhiro Iwamatsub9986be2013-10-10 09:13:41 +0900186 u8 val;
187
188 i2c_set_bus_num(3); /* PowerIC connected to ch3 */
189 i2c_init(400000, 0);
190 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
191 val |= 0x02;
192 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +0900193}