Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 3 | * Modified by Lunsheng Wang, lunsheng@sohu.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* mpc8540eval board configuration file */ |
| 25 | /* please refer to doc/README.mpc85xxads for more info */ |
| 26 | /* make sure you change the MAC address and other network params first, |
| 27 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file |
| 28 | */ |
| 29 | |
| 30 | #ifndef __CONFIG_H |
| 31 | #define __CONFIG_H |
| 32 | /* High Level Configuration Options */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 33 | #define CONFIG_BOOKE 1 /* BOOKE */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 34 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 35 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
| 36 | #define CONFIG_MPC8540 1 /* MPC8540 specific */ |
| 37 | #define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ |
| 38 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 39 | #undef CONFIG_PCI /* pci ethernet support */ |
| 40 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 41 | #define CONFIG_ENV_OVERWRITE |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 42 | |
Kumar Gala | 4d3521c | 2008-01-16 09:15:29 -0600 | [diff] [blame] | 43 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 44 | |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 45 | /* Using Localbus SDRAM to emulate flash before we can program the flash, |
| 46 | * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. |
| 47 | * Not availabe for EVAL board |
| 48 | */ |
| 49 | #undef CONFIG_RAM_AS_FLASH |
| 50 | |
| 51 | /* sysclk for MPC8540EVAL */ |
| 52 | #if defined(CONFIG_SYSCLK_66M) |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 53 | /* |
| 54 | * the oscillator on board is 66Mhz |
| 55 | * can also get 66M clock from external PCI |
| 56 | */ |
| 57 | #define CONFIG_SYS_CLK_FREQ 66000000 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 58 | #else |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 59 | #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 60 | #endif |
| 61 | |
| 62 | /* below can be toggled for performance analysis. otherwise use default */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 63 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 64 | #undef CONFIG_BTB /* toggle branch predition */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 65 | |
| 66 | #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
| 67 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 69 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 70 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 71 | |
| 72 | #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) |
| 73 | #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." |
| 74 | #endif |
| 75 | |
| 76 | /* |
| 77 | * Base addresses -- Note these are effective addresses where the |
| 78 | * actual resources get mapped (not physical addresses) |
| 79 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 81 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 82 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
| 83 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 84 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is now 256MB */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 86 | |
| 87 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 89 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 90 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 91 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 93 | |
| 94 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ |
| 96 | #define CONFIG_SYS_BR0_PRELIM 0xf8001801 /* port size 32bit */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 97 | #else /* Boot from real Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 98 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
| 99 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 /* port size 16bit */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 100 | #endif |
| 101 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_OR0_PRELIM 0xff806f67 /* 8MB Flash */ |
| 103 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 104 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ |
| 105 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 106 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ |
| 107 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ |
| 108 | #define CONFIG_SYS_FLASH_CFI 1 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 111 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 113 | #define CONFIG_SYS_RAMBOOT |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 114 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | #undef CONFIG_SYS_RAMBOOT |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 116 | #endif |
| 117 | |
Kumar Gala | 9658bec | 2008-08-26 23:52:32 -0500 | [diff] [blame] | 118 | /* DDR Setup */ |
| 119 | #define CONFIG_FSL_DDR1 |
| 120 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 121 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 122 | #define CONFIG_DDR_SPD |
| 123 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 124 | |
Kumar Gala | 9658bec | 2008-08-26 23:52:32 -0500 | [diff] [blame] | 125 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 126 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 127 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 130 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | 9658bec | 2008-08-26 23:52:32 -0500 | [diff] [blame] | 131 | #define CONFIG_VERY_BIG_RAM |
| 132 | |
| 133 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 134 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 135 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 136 | |
| 137 | /* I2C addresses of SPD EEPROMs */ |
| 138 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 139 | |
| 140 | #undef CONFIG_CLOCKS_IN_MHZ |
| 141 | |
| 142 | /* local bus definitions */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ |
| 144 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
| 145 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq divider*/ |
| 146 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 147 | #define CONFIG_SYS_LBC_LSRT 0x20000000 |
| 148 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 |
| 149 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 |
| 150 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 |
| 151 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 |
| 152 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 |
| 153 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 154 | |
| 155 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 157 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 159 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 |
| 161 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 162 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 164 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ |
| 165 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 166 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 168 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 169 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 172 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 173 | |
| 174 | /* Serial Port */ |
| 175 | #define CONFIG_CONS_INDEX 1 |
| 176 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_NS16550 |
| 178 | #define CONFIG_SYS_NS16550_SERIAL |
| 179 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 180 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 181 | #define CONFIG_BAUDRATE 115200 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 182 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 184 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 185 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 187 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 188 | |
| 189 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_HUSH_PARSER |
| 191 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 192 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 193 | #endif |
| 194 | |
Jon Loeliger | 2047672 | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 195 | /* |
| 196 | * I2C |
| 197 | */ |
| 198 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 199 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 200 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 202 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 203 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 204 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 205 | |
| 206 | /* General PCI */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
| 208 | #define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 |
| 209 | #define CONFIG_SYS_PCI_MEM_SIZE 0x20000000 |
| 210 | #define CONFIG_SYS_PCI_IO_BASE 0xe2000000 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 211 | |
| 212 | #if defined(CONFIG_PCI) |
| 213 | #define CONFIG_NET_MULTI |
| 214 | #undef CONFIG_EEPRO100 |
| 215 | #define CONFIG_TULIP |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 216 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 217 | #if !defined(CONFIG_PCI_PNP) |
| 218 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 219 | #define PCI_ENET0_MEMADDR 0xe0000000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 220 | #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 221 | #endif |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 222 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| 224 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 225 | #elif defined(CONFIG_TSEC_ENET) |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 226 | #define CONFIG_NET_MULTI 1 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 227 | #define CONFIG_MII 1 /* MII PHY management */ |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 228 | #define CONFIG_TSEC1 1 |
Andy Fleming | 10327dc | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 229 | #define CONFIG_HAS_ETH0 |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 230 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 231 | #define CONFIG_TSEC2 1 |
Andy Fleming | 10327dc | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 232 | #define CONFIG_HAS_ETH1 |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 233 | #define CONFIG_TSEC2_NAME "TSEC1" |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 234 | #define CONFIG_MPC85XX_FEC 1 |
Andy Fleming | 10327dc | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 235 | #define CONFIG_HAS_ETH2 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 236 | #define CONFIG_MPC85XX_FEC_NAME "FEC" |
| 237 | #define TSEC1_PHY_ADDR 7 |
| 238 | #define TSEC2_PHY_ADDR 4 |
| 239 | #define FEC_PHY_ADDR 2 |
| 240 | #define TSEC1_PHYIDX 0 |
| 241 | #define TSEC2_PHYIDX 0 |
| 242 | #define FEC_PHYIDX 0 |
Andy Fleming | 3a79013 | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 243 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 244 | #define TSEC2_FLAGS TSEC_GIGABIT |
| 245 | #define FEC_FLAGS 0 |
| 246 | |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 247 | /* Options are: TSEC[0-1], FEC */ |
| 248 | #define CONFIG_ETHPRIME "TSEC0" |
| 249 | |
| 250 | #define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 251 | #define INTEL_LXT971_PHY 1 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 252 | #endif |
| 253 | |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 254 | /* Environment */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 255 | #ifndef CONFIG_SYS_RAMBOOT |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 256 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 93f6d72 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 257 | #define CONFIG_ENV_IS_NOWHERE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 258 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 259 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 260 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 261 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 262 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 263 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 264 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 265 | #define CONFIG_ENV_SIZE 0x2000 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 266 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 267 | /* #define CONFIG_SYS_NO_FLASH 1 */ /* Flash is not usable now */ |
Jean-Christophe PLAGNIOL-VILLARD | 93f6d72 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 268 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 269 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 270 | #define CONFIG_ENV_SIZE 0x2000 |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 271 | #endif |
| 272 | |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 273 | #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" |
| 274 | #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 275 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 276 | |
| 277 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 279 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 280 | |
| 281 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 282 | * BOOTP options |
| 283 | */ |
| 284 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 285 | #define CONFIG_BOOTP_BOOTPATH |
| 286 | #define CONFIG_BOOTP_GATEWAY |
| 287 | #define CONFIG_BOOTP_HOSTNAME |
| 288 | |
| 289 | |
| 290 | /* |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 291 | * Command line configuration. |
| 292 | */ |
| 293 | #include <config_cmd_default.h> |
| 294 | |
| 295 | #define CONFIG_CMD_PING |
| 296 | #define CONFIG_CMD_I2C |
| 297 | |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 298 | #if defined(CONFIG_PCI) |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 299 | #define CONFIG_CMD_PCI |
Jon Loeliger | de1d0a6 | 2005-08-01 13:20:47 -0500 | [diff] [blame] | 300 | #endif |
| 301 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
Mike Frysinger | bdab39d | 2009-01-28 19:08:14 -0500 | [diff] [blame] | 303 | #undef CONFIG_CMD_SAVEENV |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 304 | #undef CONFIG_CMD_LOADS |
| 305 | #endif |
| 306 | |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 307 | |
| 308 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 309 | |
| 310 | /* |
| 311 | * Miscellaneous configurable options |
| 312 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 314 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 315 | #define CONFIG_SYS_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 316 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 317 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 318 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 319 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 320 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 321 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 322 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 323 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 324 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 325 | |
| 326 | /* |
| 327 | * For booting Linux, the board info and command line data |
| 328 | * have to be in the first 8 MB of memory, since this is |
| 329 | * the maximum mapped by the Linux kernel during initialization. |
| 330 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 331 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 332 | |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 333 | /* |
| 334 | * Internal Definitions |
| 335 | * |
| 336 | * Boot Flags |
| 337 | */ |
| 338 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 339 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 340 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 341 | #if defined(CONFIG_CMD_KGDB) |
Lunsheng Wang | b0e3294 | 2005-07-29 10:20:29 -0500 | [diff] [blame] | 342 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 343 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 344 | #endif |
| 345 | |
| 346 | /*****************************/ |
| 347 | /* Environment Configuration */ |
| 348 | /*****************************/ |
| 349 | /* The mac addresses for all ethernet interface */ |
| 350 | /* NOTE: change below for your network setting!!! */ |
| 351 | #if defined(CONFIG_TSEC_ENET) |
| 352 | #define CONFIG_ETHADDR 00:01:af:07:9b:8a |
| 353 | #define CONFIG_ETH1ADDR 00:01:af:07:9b:8b |
| 354 | #define CONFIG_ETH2ADDR 00:01:af:07:9b:8c |
| 355 | #endif |
| 356 | |
| 357 | #define CONFIG_ROOTPATH /nfsroot |
| 358 | #define CONFIG_BOOTFILE your.uImage |
| 359 | |
| 360 | #define CONFIG_SERVERIP 192.168.101.1 |
| 361 | #define CONFIG_IPADDR 192.168.101.11 |
| 362 | #define CONFIG_GATEWAYIP 192.168.101.0 |
| 363 | #define CONFIG_NETMASK 255.255.255.0 |
| 364 | |
| 365 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 366 | |
| 367 | #define CONFIG_HOSTNAME MPC8540EVAL |
| 368 | |
| 369 | #endif /* __CONFIG_H */ |