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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala39aaca12009-03-19 02:46:19 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <ppc_asm.tmpl>
Haiying Wanga52d2f82011-02-11 01:25:30 -060015#include <linux/compiler.h>
wdenk42d1f032003-10-15 23:53:47 +000016#include <asm/processor.h>
Trent Piephoada591d2008-12-03 15:16:37 -080017#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000018
Wolfgang Denkd87080b2006-03-31 18:32:53 +020019DECLARE_GLOBAL_DATA_PTR;
20
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053021
22#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24#endif
wdenk42d1f032003-10-15 23:53:47 +000025/* --------------------------------------------------------------- */
26
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053027void get_sys_info(sys_info_t *sys_info)
wdenk42d1f032003-10-15 23:53:47 +000028{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala800c73c2012-10-08 07:44:06 +000030#ifdef CONFIG_FSL_IFC
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070031 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
Kumar Gala800c73c2012-10-08 07:44:06 +000032 u32 ccr;
33#endif
Kumar Gala39aaca12009-03-19 02:46:19 -050034#ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
Timur Tabifbb9ecf2011-08-05 16:15:24 -050036 unsigned int cpu;
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +053037#ifdef CONFIG_HETROGENOUS_CLUSTERS
38 unsigned int dsp_cpu;
39 uint rcw_tmp1, rcw_tmp2;
40#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053041#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
42 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
43#endif
York Sun14109c72014-10-27 11:31:33 -070044 __maybe_unused u32 svr;
Kumar Gala39aaca12009-03-19 02:46:19 -050045
46 const u8 core_cplx_PLL[16] = {
47 [ 0] = 0, /* CC1 PPL / 1 */
48 [ 1] = 0, /* CC1 PPL / 2 */
49 [ 2] = 0, /* CC1 PPL / 4 */
50 [ 4] = 1, /* CC2 PPL / 1 */
51 [ 5] = 1, /* CC2 PPL / 2 */
52 [ 6] = 1, /* CC2 PPL / 4 */
53 [ 8] = 2, /* CC3 PPL / 1 */
54 [ 9] = 2, /* CC3 PPL / 2 */
55 [10] = 2, /* CC3 PPL / 4 */
56 [12] = 3, /* CC4 PPL / 1 */
57 [13] = 3, /* CC4 PPL / 2 */
58 [14] = 3, /* CC4 PPL / 4 */
59 };
60
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053061 const u8 core_cplx_pll_div[16] = {
Kumar Gala39aaca12009-03-19 02:46:19 -050062 [ 0] = 1, /* CC1 PPL / 1 */
63 [ 1] = 2, /* CC1 PPL / 2 */
64 [ 2] = 4, /* CC1 PPL / 4 */
65 [ 4] = 1, /* CC2 PPL / 1 */
66 [ 5] = 2, /* CC2 PPL / 2 */
67 [ 6] = 4, /* CC2 PPL / 4 */
68 [ 8] = 1, /* CC3 PPL / 1 */
69 [ 9] = 2, /* CC3 PPL / 2 */
70 [10] = 4, /* CC3 PPL / 4 */
71 [12] = 1, /* CC4 PPL / 1 */
72 [13] = 2, /* CC4 PPL / 2 */
73 [14] = 4, /* CC4 PPL / 4 */
74 };
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053075 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080076#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
77 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053078 uint rcw_tmp;
79#endif
80 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
Kumar Gala39aaca12009-03-19 02:46:19 -050081 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080082 uint mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050083
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053084 sys_info->freq_systembus = sysclk;
Priyanka Jainb1359912013-12-17 14:25:52 +053085#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
vijay rai0c12a152014-04-15 11:34:12 +053086 uint ddr_refclk_sel;
87 unsigned int porsr1_sys_clk;
88 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
89 & FSL_DCFG_PORSR1_SYSCLK_MASK;
90 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
91 sys_info->diff_sysclk = 1;
92 else
93 sys_info->diff_sysclk = 0;
94
Priyanka Jainb1359912013-12-17 14:25:52 +053095 /*
96 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
97 * are driven by separate DDR Refclock or single source
98 * differential clock.
99 */
vijay rai0c12a152014-04-15 11:34:12 +0530100 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
Priyanka Jainb1359912013-12-17 14:25:52 +0530101 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
102 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
103 /*
vijay rai0c12a152014-04-15 11:34:12 +0530104 * For single source clocking, both ddrclock and sysclock
Priyanka Jainb1359912013-12-17 14:25:52 +0530105 * are driven by differential sysclock.
106 */
vijay rai0c12a152014-04-15 11:34:12 +0530107 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
Priyanka Jainb1359912013-12-17 14:25:52 +0530108 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
vijay rai0c12a152014-04-15 11:34:12 +0530109 else
Priyanka Jainb1359912013-12-17 14:25:52 +0530110#endif
York Sun98ffa192012-10-08 07:44:31 +0000111#ifdef CONFIG_DDR_CLK_FREQ
Priyanka Jainb1359912013-12-17 14:25:52 +0530112 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
York Sun98ffa192012-10-08 07:44:31 +0000113#else
Priyanka Jainb1359912013-12-17 14:25:52 +0530114 sys_info->freq_ddrbus = sysclk;
York Sun98ffa192012-10-08 07:44:31 +0000115#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500116
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530117 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
York Sunf77329c2012-10-08 07:44:09 +0000118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
120 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
York Sunc3678b02014-03-28 15:07:27 -0700121#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
122 if (mem_pll_rat == 0) {
123 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
124 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
125 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
126 }
127#endif
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800128 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
129 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
130 * it uses 6.
York Sun14109c72014-10-27 11:31:33 -0700131 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800132 */
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800133#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
York Sun14109c72014-10-27 11:31:33 -0700134 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
135 svr = get_svr();
136 switch (SVR_SOC_VER(svr)) {
137 case SVR_T4240:
138 case SVR_T4160:
139 case SVR_T4120:
140 case SVR_T4080:
141 if (SVR_MAJ(svr) >= 2)
142 mem_pll_rat *= 2;
143 break;
144 case SVR_T2080:
145 case SVR_T2081:
146 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
147 mem_pll_rat *= 2;
148 break;
149 default:
150 break;
151 }
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800152#endif
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800153 if (mem_pll_rat > 2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530154 sys_info->freq_ddrbus *= mem_pll_rat;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800155 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530156 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -0500157
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530158 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
159 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800160 if (ratio[i] > 4)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530161 freq_c_pll[i] = sysclk * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800162 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530163 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800164 }
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530165
York Sun9a653a92012-10-08 07:44:11 +0000166#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
167 /*
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530168 * As per CHASSIS2 architeture total 12 clusters are posible and
York Sun9a653a92012-10-08 07:44:11 +0000169 * Each cluster has up to 4 cores, sharing the same PLL selection.
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530170 * The cluster clock assignment is SoC defined.
171 *
172 * Total 4 clock groups are possible with 3 PLLs each.
173 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
174 * clock group B has 3, 4, 6 and so on.
175 *
176 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
177 * depends upon the SoC architeture. Same applies to other
178 * clock groups and clusters.
179 *
York Sun9a653a92012-10-08 07:44:11 +0000180 */
181 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000182 int cluster = fsl_qoriq_core_to_cluster(cpu);
183 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
York Sun9a653a92012-10-08 07:44:11 +0000184 & 0xf;
185 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530186 cplx_pll += cc_group[cluster] - 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530187 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530188 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
York Sun9a653a92012-10-08 07:44:11 +0000189 }
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530190
191#ifdef CONFIG_HETROGENOUS_CLUSTERS
192 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
193 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
194 u32 c_pll_sel = (in_be32
195 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
196 & 0xf;
197 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
198 cplx_pll += cc_group[dsp_cluster] - 1;
199 sys_info->freq_processor_dsp[dsp_cpu] =
200 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
201 }
202#endif
203
Prabhakar Kushwahab33bd8c2014-04-21 10:47:41 +0530204#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
205 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
Sandeep Singh0cb33252013-03-25 07:33:09 +0000206#define FM1_CLK_SEL 0xe0000000
207#define FM1_CLK_SHIFT 29
Shengzhou Liuf6050792014-11-24 17:11:54 +0800208#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
209#define FM1_CLK_SEL 0x00000007
210#define FM1_CLK_SHIFT 0
Sandeep Singh0cb33252013-03-25 07:33:09 +0000211#else
York Sun9a653a92012-10-08 07:44:11 +0000212#define PME_CLK_SEL 0xe0000000
213#define PME_CLK_SHIFT 29
214#define FM1_CLK_SEL 0x1c000000
215#define FM1_CLK_SHIFT 26
Sandeep Singh0cb33252013-03-25 07:33:09 +0000216#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530217#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
Shengzhou Liuf6050792014-11-24 17:11:54 +0800218#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
219 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
220#else
York Sun9a653a92012-10-08 07:44:11 +0000221 rcw_tmp = in_be32(&gur->rcwsr[7]);
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530222#endif
Shengzhou Liuf6050792014-11-24 17:11:54 +0800223#endif
York Sun9a653a92012-10-08 07:44:11 +0000224
225#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530226#ifndef CONFIG_PME_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000227 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
228 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530229 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000230 break;
231 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530232 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000233 break;
234 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530235 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000236 break;
237 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530238 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000239 break;
240 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530241 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000242 break;
243 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530244 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000245 break;
246 default:
247 printf("Error: Unknown PME clock select!\n");
248 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530249 sys_info->freq_pme = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000250 break;
251
252 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530253#else
254 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
255
256#endif
York Sun9a653a92012-10-08 07:44:11 +0000257#endif
258
Haiying Wang990e1a82012-10-11 07:13:39 +0000259#ifdef CONFIG_SYS_DPAA_QBMAN
Shengzhou Liuf6050792014-11-24 17:11:54 +0800260#ifndef CONFIG_QBMAN_CLK_DIV
261#define CONFIG_QBMAN_CLK_DIV 2
262#endif
263 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
Haiying Wang990e1a82012-10-11 07:13:39 +0000264#endif
265
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530266#if defined(CONFIG_SYS_MAPLE)
267#define CPRI_CLK_SEL 0x1C000000
268#define CPRI_CLK_SHIFT 26
269#define CPRI_ALT_CLK_SEL 0x00007000
270#define CPRI_ALT_CLK_SHIFT 12
271
272 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
273 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
274 /* For MAPLE and CPRI frequency */
275 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
276 case 1:
277 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
278 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
279 break;
280 case 2:
281 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
282 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
283 break;
284 case 3:
285 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
286 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
287 break;
288 case 4:
289 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
290 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
291 break;
292 case 5:
293 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
294 >> CPRI_ALT_CLK_SHIFT) == 6) {
295 sys_info->freq_maple =
296 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
297 sys_info->freq_cpri =
298 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
299 }
300 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
301 >> CPRI_ALT_CLK_SHIFT) == 7) {
302 sys_info->freq_maple =
303 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
304 sys_info->freq_cpri =
305 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
306 }
307 break;
308 case 6:
309 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
310 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
311 break;
312 case 7:
313 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
314 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
315 break;
316 default:
317 printf("Error: Unknown MAPLE/CPRI clock select!\n");
318 }
319
320 /* For MAPLE ULB and eTVPE frequencies */
321#define ULB_CLK_SEL 0x00000038
322#define ULB_CLK_SHIFT 3
323#define ETVPE_CLK_SEL 0x00000007
324#define ETVPE_CLK_SHIFT 0
325
326 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
327 case 1:
328 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
329 break;
330 case 2:
331 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
332 break;
333 case 3:
334 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
335 break;
336 case 4:
337 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
338 break;
339 case 5:
340 sys_info->freq_maple_ulb = sys_info->freq_systembus;
341 break;
342 case 6:
343 sys_info->freq_maple_ulb =
344 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
345 break;
346 case 7:
347 sys_info->freq_maple_ulb =
348 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
349 break;
350 default:
351 printf("Error: Unknown MAPLE ULB clock select!\n");
352 }
353
354 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
355 case 1:
356 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
357 break;
358 case 2:
359 sys_info->freq_maple_etvpe =
360 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
361 break;
362 case 3:
363 sys_info->freq_maple_etvpe =
364 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
365 break;
366 case 4:
367 sys_info->freq_maple_etvpe =
368 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
369 break;
370 case 5:
371 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
372 break;
373 case 6:
374 sys_info->freq_maple_etvpe =
375 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
376 break;
377 case 7:
378 sys_info->freq_maple_etvpe =
379 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
380 break;
381 default:
382 printf("Error: Unknown MAPLE eTVPE clock select!\n");
383 }
384
385#endif
386
York Sun9a653a92012-10-08 07:44:11 +0000387#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530388#ifndef CONFIG_FM_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000389 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
390 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530391 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000392 break;
393 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530394 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000395 break;
396 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530397 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000398 break;
399 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530400 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000401 break;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000402 case 5:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530403 sys_info->freq_fman[0] = sys_info->freq_systembus;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000404 break;
York Sun9a653a92012-10-08 07:44:11 +0000405 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530406 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000407 break;
408 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530409 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000410 break;
411 default:
412 printf("Error: Unknown FMan1 clock select!\n");
413 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530414 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000415 break;
416 }
417#if (CONFIG_SYS_NUM_FMAN) == 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530418#ifdef CONFIG_SYS_FM2_CLK
York Sun9a653a92012-10-08 07:44:11 +0000419#define FM2_CLK_SEL 0x00000038
420#define FM2_CLK_SHIFT 3
421 rcw_tmp = in_be32(&gur->rcwsr[15]);
422 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
423 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530424 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
York Sun9a653a92012-10-08 07:44:11 +0000425 break;
426 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530427 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000428 break;
429 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530430 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000431 break;
432 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530433 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000434 break;
Shaohui Xiec1015c62013-11-28 13:52:51 +0800435 case 5:
436 sys_info->freq_fman[1] = sys_info->freq_systembus;
437 break;
York Sun9a653a92012-10-08 07:44:11 +0000438 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530439 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000440 break;
441 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530442 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000443 break;
444 default:
445 printf("Error: Unknown FMan2 clock select!\n");
446 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530447 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000448 break;
449 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530450#endif
York Sun9a653a92012-10-08 07:44:11 +0000451#endif /* CONFIG_SYS_NUM_FMAN == 2 */
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530452#else
453 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
454#endif
455#endif
York Sun9a653a92012-10-08 07:44:11 +0000456
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800457#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
458#if defined(CONFIG_PPC_T2080)
459#define ESDHC_CLK_SEL 0x00000007
460#define ESDHC_CLK_SHIFT 0
461#define ESDHC_CLK_RCWSR 15
462#else /* Support T1040 T1024 by now */
463#define ESDHC_CLK_SEL 0xe0000000
464#define ESDHC_CLK_SHIFT 29
465#define ESDHC_CLK_RCWSR 7
466#endif
467 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
468 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
469 case 1:
470 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
471 break;
472 case 2:
473 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
474 break;
475 case 3:
476 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
477 break;
478#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
479 case 4:
480 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
481 break;
482#if defined(CONFIG_PPC_T2080)
483 case 5:
484 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
485 break;
486#endif
487 case 6:
488 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
489 break;
490 case 7:
491 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
492 break;
493#endif
494 default:
495 sys_info->freq_sdhc = 0;
496 printf("Error: Unknown SDHC peripheral clock select!\n");
497 }
498#endif
York Sun9a653a92012-10-08 07:44:11 +0000499#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
500
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500501 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000502 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
503 & 0xf;
Kumar Gala39aaca12009-03-19 02:46:19 -0500504 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
505
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530506 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530507 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
Kumar Gala39aaca12009-03-19 02:46:19 -0500508 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500509#define PME_CLK_SEL 0x80000000
510#define FM1_CLK_SEL 0x40000000
511#define FM2_CLK_SEL 0x20000000
Kumar Galab5c87532011-02-16 02:03:29 -0600512#define HWA_ASYNC_DIV 0x04000000
513#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
514#define HWA_CC_PLL 1
Timur Tabi49054432012-10-05 11:09:19 +0000515#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
516#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600517#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
Wolfgang Denkcd6881b2011-05-19 22:21:41 +0200518#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600519#else
520#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
521#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500522 rcw_tmp = in_be32(&gur->rcwsr[7]);
523
524#ifdef CONFIG_SYS_DPAA_PME
Kumar Galab5c87532011-02-16 02:03:29 -0600525 if (rcw_tmp & PME_CLK_SEL) {
526 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530527 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600528 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530529 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600530 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530531 sys_info->freq_pme = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600532 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500533#endif
534
535#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Galab5c87532011-02-16 02:03:29 -0600536 if (rcw_tmp & FM1_CLK_SEL) {
537 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530538 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600539 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530540 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600541 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530542 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600543 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500544#if (CONFIG_SYS_NUM_FMAN) == 2
Kumar Galab5c87532011-02-16 02:03:29 -0600545 if (rcw_tmp & FM2_CLK_SEL) {
546 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530547 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600548 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530549 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600550 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530551 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600552 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500553#endif
554#endif
555
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000556#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530557 sys_info->freq_qman = sys_info->freq_systembus / 2;
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000558#endif
559
York Sun9a653a92012-10-08 07:44:11 +0000560#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
561
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800562#ifdef CONFIG_U_QE
563 sys_info->freq_qe = sys_info->freq_systembus / 2;
564#endif
565
York Sun9a653a92012-10-08 07:44:11 +0000566#else /* CONFIG_FSL_CORENET */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530567 uint plat_ratio, e500_ratio, half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500568 int i;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400569#ifdef CONFIG_QE
Haiying Wanga52d2f82011-02-11 01:25:30 -0600570 __maybe_unused u32 qe_ratio;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400571#endif
wdenk42d1f032003-10-15 23:53:47 +0000572
573 plat_ratio = (gur->porpllsr) & 0x0000003e;
574 plat_ratio >>= 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530575 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500576
577 /* Divide before multiply to avoid integer
578 * overflow for processor speeds above 2GHz */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530579 half_freq_systembus = sys_info->freq_systembus/2;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530580 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500581 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530582 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500583 }
James Yanga3e77fa2008-02-08 18:05:08 -0600584
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530585 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
586 sys_info->freq_ddrbus = sys_info->freq_systembus;
Kumar Galad4357932007-12-07 04:59:26 -0600587
588#ifdef CONFIG_DDR_CLK_FREQ
589 {
Jason Jinc0391112008-09-27 14:40:57 +0800590 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
591 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galad4357932007-12-07 04:59:26 -0600592 if (ddr_ratio != 0x7)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530593 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
Kumar Galad4357932007-12-07 04:59:26 -0600594 }
595#endif
Trent Piephoada591d2008-12-03 15:16:37 -0800596
Haiying Wangb3d7f202009-05-20 12:30:29 -0400597#ifdef CONFIG_QE
York Sunbe7bebe2012-08-10 11:07:26 +0000598#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530599 sys_info->freq_qe = sys_info->freq_systembus;
Haiying Wanga52d2f82011-02-11 01:25:30 -0600600#else
Haiying Wangb3d7f202009-05-20 12:30:29 -0400601 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
602 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530603 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400604#endif
Haiying Wanga52d2f82011-02-11 01:25:30 -0600605#endif
Haiying Wangb3d7f202009-05-20 12:30:29 -0400606
Haiying Wang24995d82011-01-20 22:26:31 +0000607#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530608 sys_info->freq_fman[0] = sys_info->freq_systembus;
Haiying Wang24995d82011-01-20 22:26:31 +0000609#endif
610
611#endif /* CONFIG_FSL_CORENET */
612
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530613#if defined(CONFIG_FSL_LBC)
York Sun9a653a92012-10-08 07:44:11 +0000614 uint lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800615#if defined(CONFIG_SYS_LBC_LCRR)
616 /* We will program LCRR to this value later */
617 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
618#else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500619 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
Trent Piephoada591d2008-12-03 15:16:37 -0800620#endif
621 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
Dave Liu0fd2fa62009-11-17 20:49:05 +0800622#if defined(CONFIG_FSL_CORENET)
623 /* If this is corenet based SoC, bit-representation
624 * for four times the clock divider values.
625 */
626 lcrr_div *= 4;
627#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
Trent Piephoada591d2008-12-03 15:16:37 -0800628 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
629 /*
630 * Yes, the entire PQ38 family use the same
631 * bit-representation for twice the clock divider values.
632 */
633 lcrr_div *= 2;
634#endif
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530635 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800636 } else {
637 /* In case anyone cares what the unknown value is */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530638 sys_info->freq_localbus = lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800639 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530640#endif
Kumar Gala800c73c2012-10-08 07:44:06 +0000641
642#if defined(CONFIG_FSL_IFC)
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700643 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
Kumar Gala800c73c2012-10-08 07:44:06 +0000644 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
645
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530646 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
Kumar Gala800c73c2012-10-08 07:44:06 +0000647#endif
wdenk42d1f032003-10-15 23:53:47 +0000648}
649
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500650
wdenk42d1f032003-10-15 23:53:47 +0000651int get_clocks (void)
652{
wdenk42d1f032003-10-15 23:53:47 +0000653 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -0500654#ifdef CONFIG_MPC8544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200655 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi88353a92008-04-04 11:15:58 -0500656#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500657#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200658 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000659 uint sccr, dfbrg;
660
661 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600662 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
663 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +0000664 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
665#endif
666 get_sys_info (&sys_info);
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530667 gd->cpu_clk = sys_info.freq_processor[0];
668 gd->bus_clk = sys_info.freq_systembus;
669 gd->mem_clk = sys_info.freq_ddrbus;
670 gd->arch.lbc_clk = sys_info.freq_localbus;
Timur Tabi88353a92008-04-04 11:15:58 -0500671
Haiying Wangb3d7f202009-05-20 12:30:29 -0400672#ifdef CONFIG_QE
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530673 gd->arch.qe_clk = sys_info.freq_qe;
Simon Glass45bae2e2012-12-13 20:48:50 +0000674 gd->arch.brg_clk = gd->arch.qe_clk / 2;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400675#endif
Timur Tabi88353a92008-04-04 11:15:58 -0500676 /*
677 * The base clock for I2C depends on the actual SOC. Unfortunately,
678 * there is no pattern that can be used to determine the frequency, so
679 * the only choice is to look up the actual SOC number and use the value
680 * for that SOC. This information is taken from application note
681 * AN2919.
682 */
683#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
Tang Yuantianf62b1232013-09-06 10:45:40 +0800684 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
685 defined(CONFIG_P1022)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530686 gd->arch.i2c1_clk = sys_info.freq_systembus;
Timur Tabi88353a92008-04-04 11:15:58 -0500687#elif defined(CONFIG_MPC8544)
688 /*
689 * On the 8544, the I2C clock is the same as the SEC clock. This can be
690 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
691 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
692 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
693 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
694 */
695 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530696 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
Kumar Gala42653b82008-10-16 21:58:49 -0500697 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530698 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500699#else
700 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530701 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500702#endif
Simon Glass609e6ec2012-12-13 20:48:49 +0000703 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600704
Dipen Dudhat6b9ea082009-09-01 17:27:00 +0530705#if defined(CONFIG_FSL_ESDHC)
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800706#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
707 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
708#else
Priyanka Jain7d640e92011-02-08 15:45:25 +0530709#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
710 defined(CONFIG_P1014)
Simon Glasse9adeca2012-12-13 20:49:05 +0000711 gd->arch.sdhc_clk = gd->bus_clk;
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400712#else
Simon Glasse9adeca2012-12-13 20:49:05 +0000713 gd->arch.sdhc_clk = gd->bus_clk / 2;
Kumar Galaef50d6c2008-08-12 11:14:19 -0500714#endif
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800715#endif
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400716#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galaef50d6c2008-08-12 11:14:19 -0500717
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500718#if defined(CONFIG_CPM2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530719 gd->arch.vco_out = 2*sys_info.freq_systembus;
Simon Glass748cd052012-12-13 20:48:46 +0000720 gd->arch.cpm_clk = gd->arch.vco_out / 2;
721 gd->arch.scc_clk = gd->arch.vco_out / 4;
722 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
wdenk42d1f032003-10-15 23:53:47 +0000723#endif
724
725 if(gd->cpu_clk != 0) return (0);
726 else return (1);
727}
728
729
730/********************************************
731 * get_bus_freq
732 * return system bus freq in Hz
733 *********************************************/
734ulong get_bus_freq (ulong dummy)
735{
James Yanga3e77fa2008-02-08 18:05:08 -0600736 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000737}
Kumar Galad4357932007-12-07 04:59:26 -0600738
739/********************************************
740 * get_ddr_freq
741 * return ddr bus freq in Hz
742 *********************************************/
743ulong get_ddr_freq (ulong dummy)
744{
James Yanga3e77fa2008-02-08 18:05:08 -0600745 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600746}