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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08005 */
6
7#include <common.h>
Vikas Manochafd03b832017-02-12 10:25:46 -08008#include <clk.h>
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08009#include <dm.h>
10#include <asm/io.h>
11#include <serial.h>
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090012#include <asm/arch/stm32.h>
Patrice Chotardae74de02018-01-12 09:23:49 +010013#include "serial_stm32.h"
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080014
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080015static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
16{
Patrice Chotard60a996b2017-09-27 15:44:50 +020017 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
18 bool stm32f4 = plat->uart_info->stm32f4;
19 fdt_addr_t base = plat->base;
Patrice Chotard27265ce2017-07-18 09:29:08 +020020 u32 int_div, mantissa, fraction, oversampling;
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090021
Patrice Chotard27265ce2017-07-18 09:29:08 +020022 int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020023
24 if (int_div < 16) {
25 oversampling = 8;
Patrice Chotard60a996b2017-09-27 15:44:50 +020026 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020027 } else {
28 oversampling = 16;
Patrice Chotard60a996b2017-09-27 15:44:50 +020029 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020030 }
31
32 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
33 fraction = int_div % oversampling;
34
Patrice Chotard60a996b2017-09-27 15:44:50 +020035 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080036
37 return 0;
38}
39
40static int stm32_serial_getc(struct udevice *dev)
41{
Patrice Chotard60a996b2017-09-27 15:44:50 +020042 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
43 bool stm32f4 = plat->uart_info->stm32f4;
44 fdt_addr_t base = plat->base;
Patrice Chotard7b3b74d2018-04-20 08:59:06 +020045 u32 isr = readl(base + ISR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080046
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020047 if ((isr & USART_ISR_FLAG_RXNE) == 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080048 return -EAGAIN;
49
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020050 if (isr & USART_ISR_FLAG_ORE) {
Patrice Chotard7b3b74d2018-04-20 08:59:06 +020051 if (!stm32f4)
52 setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
53 else
54 readl(base + RDR_OFFSET(stm32f4));
55 return -EIO;
56 }
57
Patrice Chotard60a996b2017-09-27 15:44:50 +020058 return readl(base + RDR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080059}
60
61static int stm32_serial_putc(struct udevice *dev, const char c)
62{
Patrice Chotard60a996b2017-09-27 15:44:50 +020063 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
64 bool stm32f4 = plat->uart_info->stm32f4;
65 fdt_addr_t base = plat->base;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080066
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020067 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_FLAG_TXE) == 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080068 return -EAGAIN;
69
Patrice Chotard60a996b2017-09-27 15:44:50 +020070 writel(c, base + TDR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080071
72 return 0;
73}
74
75static int stm32_serial_pending(struct udevice *dev, bool input)
76{
Patrice Chotard60a996b2017-09-27 15:44:50 +020077 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
78 bool stm32f4 = plat->uart_info->stm32f4;
79 fdt_addr_t base = plat->base;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080080
81 if (input)
Patrice Chotard60a996b2017-09-27 15:44:50 +020082 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020083 USART_ISR_FLAG_RXNE ? 1 : 0;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080084 else
Patrice Chotard60a996b2017-09-27 15:44:50 +020085 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020086 USART_ISR_FLAG_TXE ? 0 : 1;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080087}
88
89static int stm32_serial_probe(struct udevice *dev)
90{
Patrice Chotard60a996b2017-09-27 15:44:50 +020091 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
Patrice Chotard9a212d72017-09-27 15:44:53 +020092 struct clk clk;
Patrice Chotard60a996b2017-09-27 15:44:50 +020093 fdt_addr_t base = plat->base;
Patrice Chotard9a212d72017-09-27 15:44:53 +020094 int ret;
Patrice Chotard60a996b2017-09-27 15:44:50 +020095 bool stm32f4;
96 u8 uart_enable_bit;
97
98 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
99 stm32f4 = plat->uart_info->stm32f4;
100 uart_enable_bit = plat->uart_info->uart_enable_bit;
Vikas Manochafd03b832017-02-12 10:25:46 -0800101
Vikas Manochafd03b832017-02-12 10:25:46 -0800102 ret = clk_get_by_index(dev, 0, &clk);
103 if (ret < 0)
104 return ret;
105
106 ret = clk_enable(&clk);
107 if (ret) {
108 dev_err(dev, "failed to enable clock\n");
109 return ret;
110 }
Vikas Manochafd03b832017-02-12 10:25:46 -0800111
Patrice Chotard27265ce2017-07-18 09:29:08 +0200112 plat->clock_rate = clk_get_rate(&clk);
113 if (plat->clock_rate < 0) {
114 clk_disable(&clk);
115 return plat->clock_rate;
116 };
117
Patrice Chotard7b3b74d2018-04-20 08:59:06 +0200118 /* Disable uart-> enable fifo-> enable uart */
Patrice Chotard60a996b2017-09-27 15:44:50 +0200119 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
120 BIT(uart_enable_bit));
Patrice Chotard2a7ecc52017-09-27 15:44:51 +0200121 if (plat->uart_info->has_fifo)
122 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
Patrice Chotard60a996b2017-09-27 15:44:50 +0200123 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
124 BIT(uart_enable_bit));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800125
126 return 0;
127}
128
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800129static const struct udevice_id stm32_serial_id[] = {
Patrice Chotard6c30f152017-09-27 15:44:52 +0200130 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
Patrice Chotard2a7ecc52017-09-27 15:44:51 +0200131 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
132 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800133 {}
134};
135
136static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
137{
138 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800139
Patrice Chotard60a996b2017-09-27 15:44:50 +0200140 plat->base = devfdt_get_addr(dev);
141 if (plat->base == FDT_ADDR_T_NONE)
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800142 return -EINVAL;
143
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800144 return 0;
145}
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800146
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800147static const struct dm_serial_ops stm32_serial_ops = {
148 .putc = stm32_serial_putc,
149 .pending = stm32_serial_pending,
150 .getc = stm32_serial_getc,
151 .setbrg = stm32_serial_setbrg,
152};
153
154U_BOOT_DRIVER(serial_stm32) = {
Patrice Chotardae74de02018-01-12 09:23:49 +0100155 .name = "serial_stm32",
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800156 .id = UCLASS_SERIAL,
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800157 .of_match = of_match_ptr(stm32_serial_id),
158 .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
159 .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800160 .ops = &stm32_serial_ops,
161 .probe = stm32_serial_probe,
162 .flags = DM_FLAG_PRE_RELOC,
163};