| Sekhar Nori | 8ed5885 | 2010-01-27 11:10:40 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * Register definitions for the DaVinci SPI Controller |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #ifndef _DAVINCI_SPI_H_ |
| 23 | #define _DAVINCI_SPI_H_ |
| 24 | |
| 25 | struct davinci_spi_regs { |
| 26 | dv_reg gcr0; /* 0x00 */ |
| 27 | dv_reg gcr1; /* 0x04 */ |
| 28 | dv_reg int0; /* 0x08 */ |
| 29 | dv_reg lvl; /* 0x0c */ |
| 30 | dv_reg flg; /* 0x10 */ |
| 31 | dv_reg pc0; /* 0x14 */ |
| 32 | dv_reg pc1; /* 0x18 */ |
| 33 | dv_reg pc2; /* 0x1c */ |
| 34 | dv_reg pc3; /* 0x20 */ |
| 35 | dv_reg pc4; /* 0x24 */ |
| 36 | dv_reg pc5; /* 0x28 */ |
| 37 | dv_reg rsvd[3]; |
| 38 | dv_reg dat0; /* 0x38 */ |
| 39 | dv_reg dat1; /* 0x3c */ |
| 40 | dv_reg buf; /* 0x40 */ |
| 41 | dv_reg emu; /* 0x44 */ |
| 42 | dv_reg delay; /* 0x48 */ |
| 43 | dv_reg def; /* 0x4c */ |
| 44 | dv_reg fmt0; /* 0x50 */ |
| 45 | dv_reg fmt1; /* 0x54 */ |
| 46 | dv_reg fmt2; /* 0x58 */ |
| 47 | dv_reg fmt3; /* 0x5c */ |
| 48 | dv_reg intvec0; /* 0x60 */ |
| 49 | dv_reg intvec1; /* 0x64 */ |
| 50 | }; |
| 51 | |
| 52 | #define BIT(x) (1 << (x)) |
| 53 | |
| 54 | /* SPIGCR0 */ |
| 55 | #define SPIGCR0_SPIENA_MASK 0x1 |
| 56 | #define SPIGCR0_SPIRST_MASK 0x0 |
| 57 | |
| 58 | /* SPIGCR0 */ |
| 59 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
| 60 | #define SPIGCR1_MASTER_MASK BIT(0) |
| 61 | #define SPIGCR1_SPIENA_MASK BIT(24) |
| 62 | |
| 63 | /* SPIPC0 */ |
| 64 | #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ |
| 65 | #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ |
| 66 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ |
| 67 | #define SPIPC0_EN0FUN_MASK BIT(0) |
| 68 | |
| 69 | /* SPIFMT0 */ |
| 70 | #define SPIFMT_SHIFTDIR_SHIFT 20 |
| 71 | #define SPIFMT_POLARITY_SHIFT 17 |
| 72 | #define SPIFMT_PHASE_SHIFT 16 |
| 73 | #define SPIFMT_PRESCALE_SHIFT 8 |
| 74 | |
| 75 | /* SPIDAT1 */ |
| 76 | #define SPIDAT1_CSHOLD_SHIFT 28 |
| 77 | #define SPIDAT1_CSNR_SHIFT 16 |
| 78 | |
| 79 | /* SPIDELAY */ |
| 80 | #define SPI_C2TDELAY_SHIFT 24 |
| 81 | #define SPI_T2CDELAY_SHIFT 16 |
| 82 | |
| 83 | /* SPIBUF */ |
| 84 | #define SPIBUF_RXEMPTY_MASK BIT(31) |
| 85 | #define SPIBUF_TXFULL_MASK BIT(29) |
| 86 | |
| 87 | /* SPIDEF */ |
| 88 | #define SPIDEF_CSDEF0_MASK BIT(0) |
| 89 | |
| 90 | struct davinci_spi_slave { |
| 91 | struct spi_slave slave; |
| 92 | struct davinci_spi_regs *regs; |
| 93 | unsigned int freq; |
| 94 | }; |
| 95 | |
| 96 | static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) |
| 97 | { |
| 98 | return container_of(slave, struct davinci_spi_slave, slave); |
| 99 | } |
| 100 | |
| 101 | #endif /* _DAVINCI_SPI_H_ */ |