unsik Kim | 75eb82e | 2009-02-25 11:31:24 +0900 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 mGine co. |
| 3 | * unsik Kim <donari75@gmail.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __MG_DISK_PRV_H__ |
| 25 | #define __MG_DISK_PRV_H__ |
| 26 | |
| 27 | #include <mg_disk.h> |
| 28 | |
| 29 | /* name for block device */ |
| 30 | #define MG_DISK_NAME "mgd" |
| 31 | /* name for platform device */ |
| 32 | #define MG_DEV_NAME "mg_disk" |
| 33 | |
| 34 | #define MG_DISK_MAJ 240 |
| 35 | #define MG_DISK_MAX_PART 16 |
| 36 | #define MG_SECTOR_SIZE 512 |
| 37 | #define MG_SECTOR_SIZE_MASK (512 - 1) |
| 38 | #define MG_SECTOR_SIZE_SHIFT (9) |
| 39 | #define MG_MAX_SECTS 256 |
| 40 | |
| 41 | /* Register offsets */ |
| 42 | #define MG_BUFF_OFFSET 0x8000 |
| 43 | #define MG_STORAGE_BUFFER_SIZE 0x200 |
| 44 | #define MG_REG_OFFSET 0xC000 |
| 45 | #define MG_REG_FEATURE (MG_REG_OFFSET + 2) /* write case */ |
| 46 | #define MG_REG_ERROR (MG_REG_OFFSET + 2) /* read case */ |
| 47 | #define MG_REG_SECT_CNT (MG_REG_OFFSET + 4) |
| 48 | #define MG_REG_SECT_NUM (MG_REG_OFFSET + 6) |
| 49 | #define MG_REG_CYL_LOW (MG_REG_OFFSET + 8) |
| 50 | #define MG_REG_CYL_HIGH (MG_REG_OFFSET + 0xA) |
| 51 | #define MG_REG_DRV_HEAD (MG_REG_OFFSET + 0xC) |
| 52 | #define MG_REG_COMMAND (MG_REG_OFFSET + 0xE) /* write case */ |
| 53 | #define MG_REG_STATUS (MG_REG_OFFSET + 0xE) /* read case */ |
| 54 | #define MG_REG_DRV_CTRL (MG_REG_OFFSET + 0x10) |
| 55 | #define MG_REG_BURST_CTRL (MG_REG_OFFSET + 0x12) |
| 56 | |
| 57 | /* "Drive Select/Head Register" bit values */ |
| 58 | #define MG_REG_HEAD_MUST_BE_ON 0xA0 /* These 2 bits are always on */ |
| 59 | #define MG_REG_HEAD_DRIVE_MASTER (0x00 | MG_REG_HEAD_MUST_BE_ON) |
| 60 | #define MG_REG_HEAD_DRIVE_SLAVE (0x10 | MG_REG_HEAD_MUST_BE_ON) |
| 61 | #define MG_REG_HEAD_LBA_MODE (0x40 | MG_REG_HEAD_MUST_BE_ON) |
| 62 | |
| 63 | |
| 64 | /* "Device Control Register" bit values */ |
| 65 | #define MG_REG_CTRL_INTR_ENABLE 0x0 |
| 66 | #define MG_REG_CTRL_INTR_DISABLE (0x1 << 1) |
| 67 | #define MG_REG_CTRL_RESET (0x1 << 2) |
| 68 | #define MG_REG_CTRL_INTR_POLA_ACTIVE_HIGH 0x0 |
| 69 | #define MG_REG_CTRL_INTR_POLA_ACTIVE_LOW (0x1 << 4) |
| 70 | #define MG_REG_CTRL_DPD_POLA_ACTIVE_LOW 0x0 |
| 71 | #define MG_REG_CTRL_DPD_POLA_ACTIVE_HIGH (0x1 << 5) |
| 72 | #define MG_REG_CTRL_DPD_DISABLE 0x0 |
| 73 | #define MG_REG_CTRL_DPD_ENABLE (0x1 << 6) |
| 74 | |
| 75 | /* Status register bit */ |
| 76 | /* error bit in status register */ |
| 77 | #define MG_REG_STATUS_BIT_ERROR 0x01 |
| 78 | /* corrected error in status register */ |
| 79 | #define MG_REG_STATUS_BIT_CORRECTED_ERROR 0x04 |
| 80 | /* data request bit in status register */ |
| 81 | #define MG_REG_STATUS_BIT_DATA_REQ 0x08 |
| 82 | /* DSC - Drive Seek Complete */ |
| 83 | #define MG_REG_STATUS_BIT_SEEK_DONE 0x10 |
| 84 | /* DWF - Drive Write Fault */ |
| 85 | #define MG_REG_STATUS_BIT_WRITE_FAULT 0x20 |
| 86 | #define MG_REG_STATUS_BIT_READY 0x40 |
| 87 | #define MG_REG_STATUS_BIT_BUSY 0x80 |
| 88 | |
| 89 | /* handy status */ |
| 90 | #define MG_STAT_READY (MG_REG_STATUS_BIT_READY | MG_REG_STATUS_BIT_SEEK_DONE) |
| 91 | #define MG_READY_OK(s) (((s) & (MG_STAT_READY | \ |
| 92 | (MG_REG_STATUS_BIT_BUSY | \ |
| 93 | MG_REG_STATUS_BIT_WRITE_FAULT | \ |
| 94 | MG_REG_STATUS_BIT_ERROR))) == MG_STAT_READY) |
| 95 | |
| 96 | /* Error register */ |
| 97 | #define MG_REG_ERR_AMNF 0x01 |
| 98 | #define MG_REG_ERR_ABRT 0x04 |
| 99 | #define MG_REG_ERR_IDNF 0x10 |
| 100 | #define MG_REG_ERR_UNC 0x40 |
| 101 | #define MG_REG_ERR_BBK 0x80 |
| 102 | |
| 103 | /* error code for others */ |
| 104 | #define MG_ERR_NONE 0 |
| 105 | #define MG_ERR_TIMEOUT 0x100 |
| 106 | #define MG_ERR_INIT_STAT 0x101 |
| 107 | #define MG_ERR_TRANSLATION 0x102 |
| 108 | #define MG_ERR_CTRL_RST 0x103 |
| 109 | #define MG_ERR_NO_DRV_DATA 0x104 |
| 110 | |
| 111 | #define MG_MAX_ERRORS 16 /* Max read/write errors/sector */ |
| 112 | #define MG_RESET_FREQ 4 /* Reset controller every 4th retry */ |
| 113 | |
| 114 | /* command */ |
| 115 | #define MG_CMD_RD 0x20 |
| 116 | #define MG_CMD_WR 0x30 |
| 117 | #define MG_CMD_SLEEP 0x99 |
| 118 | #define MG_CMD_WAKEUP 0xC3 |
| 119 | #define MG_CMD_ID 0xEC |
| 120 | #define MG_CMD_WR_CONF 0x3C |
| 121 | #define MG_CMD_RD_CONF 0x40 |
| 122 | |
| 123 | union mg_uniwb{ |
| 124 | u16 w; |
| 125 | u8 b[2]; |
| 126 | }; |
| 127 | |
| 128 | /* main structure for mflash driver */ |
| 129 | struct mg_host { |
| 130 | struct mg_drv_data *drv_data; |
| 131 | /* for future use */ |
| 132 | }; |
| 133 | |
| 134 | /* |
| 135 | * Debugging macro and defines |
| 136 | */ |
| 137 | #undef DO_MG_DEBUG |
| 138 | #ifdef DO_MG_DEBUG |
| 139 | # define MG_DBG(fmt, args...) printf("%s:%d "fmt"\n", __func__, __LINE__,##args) |
| 140 | #else /* CONFIG_MG_DEBUG */ |
| 141 | # define MG_DBG(fmt, args...) do { } while(0) |
| 142 | #endif /* CONFIG_MG_DEBUG */ |
| 143 | |
| 144 | #endif |