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wdenke0648062002-08-20 00:12:21 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
37#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 9600
43#if 0
44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
45#else
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47#endif
48
49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
50
51#define CONFIG_BOARD_TYPES 1 /* support board types */
52
53#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
54
55#undef CONFIG_BOOTARGS
56#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020057 "bootp; " \
58 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke0648062002-08-20 00:12:21 +000060 "bootm"
61
62#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64
65#undef CONFIG_WATCHDOG /* watchdog disabled */
66
Jon Loeliger48d5d102007-07-04 22:32:25 -050067
68/*
69 * Command line configuration.
70 */
71#include <config_cmd_default.h>
72
wdenke0648062002-08-20 00:12:21 +000073
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050074/*
75 * BOOTP options
76 */
77#define CONFIG_BOOTP_SUBNETMASK
78#define CONFIG_BOOTP_GATEWAY
79#define CONFIG_BOOTP_HOSTNAME
80#define CONFIG_BOOTP_BOOTPATH
81
wdenke0648062002-08-20 00:12:21 +000082
wdenke0648062002-08-20 00:12:21 +000083/*
84 * Miscellaneous configurable options
85 */
86#define CFG_LONGHELP /* undef to save memory */
87#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger48d5d102007-07-04 22:32:25 -050088#if defined(CONFIG_CMD_KGDB)
wdenke0648062002-08-20 00:12:21 +000089#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
90#else
91#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
92#endif
93#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
94#define CFG_MAXARGS 16 /* max number of command args */
95#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
96
97#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
98#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
99
100#define CFG_LOAD_ADDR 0x00100000 /* default load address */
101
102#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
103
104#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
105
106#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
107
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200108#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
wdenke0648062002-08-20 00:12:21 +0000109/*
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
113 */
114/*-----------------------------------------------------------------------
115 * Internal Memory Mapped Register
116 */
117#define CFG_IMMR 0xFF000000 /* Non-Standard value! */
118
119/*-----------------------------------------------------------------------
120 * Definitions for initial stack pointer and data area (in DPRAM)
121 */
122#define CFG_INIT_RAM_ADDR CFG_IMMR
123#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
124#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
125#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
126#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
127
128/*-----------------------------------------------------------------------
129 * Start addresses for the final memory configuration
130 * (Set up by the startup code)
131 * Please note that CFG_SDRAM_BASE _must_ start at 0
132 */
133#define CFG_SDRAM_BASE 0x00000000
134#define CFG_FLASH_BASE 0xFE000000
135#ifdef DEBUG
136#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
137#else
138#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
139#endif
140#define CFG_MONITOR_BASE CFG_FLASH_BASE
141#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
142
143/*
144 * For booting Linux, the board info and command line data
145 * have to be in the first 8 MB of memory, since this is
146 * the maximum mapped by the Linux kernel during initialization.
147 */
148#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
149/*-----------------------------------------------------------------------
150 * FLASH organization
151 */
152#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
153#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
154
155#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
156#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
157
158#define CFG_ENV_IS_IN_FLASH 1
159#define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
160#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
161/*-----------------------------------------------------------------------
162 * Cache Configuration
163 */
164#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500165#if defined(CONFIG_CMD_KGDB)
wdenke0648062002-08-20 00:12:21 +0000166#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
167#endif
168
169/*-----------------------------------------------------------------------
170 * SYPCR - System Protection Control 11-9
171 * SYPCR can only be written once after reset!
172 *-----------------------------------------------------------------------
173 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
174 * +0x0004
175 */
176#if defined(CONFIG_WATCHDOG)
177#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
178 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
179#else
180#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
181#endif
182
183/*-----------------------------------------------------------------------
184 * SIUMCR - SIU Module Configuration 11-6
185 *-----------------------------------------------------------------------
186 * +0x0000 => 0x000000C0
187 */
188#define CFG_SIUMCR 0
189
190/*-----------------------------------------------------------------------
191 * TBSCR - Time Base Status and Control 11-26
192 *-----------------------------------------------------------------------
193 * Clear Reference Interrupt Status, Timebase freezing enabled
194 * +0x0200 => 0x00C2
195 */
196#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
197
198/*-----------------------------------------------------------------------
199 * PISCR - Periodic Interrupt Status and Control 11-31
200 *-----------------------------------------------------------------------
201 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
202 * +0x0240 => 0x0082
203 */
204#define CFG_PISCR (PISCR_PS | PISCR_PITF)
205
206/*-----------------------------------------------------------------------
207 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
208 *-----------------------------------------------------------------------
209 * Reset PLL lock status sticky bit, timer expired status bit and timer
210 * interrupt status bit, set PLL multiplication factor !
211 */
212/* +0x0286 => 0x00B0D0C0 */
213#define CFG_PLPRCR \
214 ( (11 << PLPRCR_MF_SHIFT) | \
215 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
216 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
217 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
218 )
219
220/*-----------------------------------------------------------------------
221 * SCCR - System Clock and reset Control Register 15-27
222 *-----------------------------------------------------------------------
223 * Set clock output, timebase and RTC source and divider,
224 * power management and some other internal clocks
225 */
226#define SCCR_MASK SCCR_EBDF11
227/* +0x0282 => 0x03800000 */
228#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
229 SCCR_RTDIV | SCCR_RTSEL | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200230 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
wdenke0648062002-08-20 00:12:21 +0000231 SCCR_EBDF00 | SCCR_DFSYNC00 | \
232 SCCR_DFBRG00 | SCCR_DFNL000 | \
233 SCCR_DFNH000)
234
235/*-----------------------------------------------------------------------
236 * RTCSC - Real-Time Clock Status and Control Register 11-27
237 *-----------------------------------------------------------------------
238 */
239/* +0x0220 => 0x00C3 */
240#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
241
242
243/*-----------------------------------------------------------------------
244 * RCCR - RISC Controller Configuration Register 19-4
245 *-----------------------------------------------------------------------
246 */
247/* +0x09C4 => TIMEP=1 */
248#define CFG_RCCR 0x0100
249
250/*-----------------------------------------------------------------------
251 * RMDS - RISC Microcode Development Support Control Register
252 *-----------------------------------------------------------------------
253 */
254#define CFG_RMDS 0
255
256/*-----------------------------------------------------------------------
257 *
258 *-----------------------------------------------------------------------
259 *
260 */
wdenke0648062002-08-20 00:12:21 +0000261#define CFG_DER 0
262
263/*
264 * Init Memory Controller:
265 *
266 * BR0 and OR0 (FLASH)
267 */
268
269#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
270
271/* used to re-map FLASH
272 * restrict access enough to keep SRAM working (if any)
273 * but not too much to meddle with FLASH accesses
274 */
275/* allow for max 4 MB of Flash */
276#define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
277#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
278
279/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
280#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
281 OR_SCY_5_CLK | OR_TRLX)
282
283#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
284#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
285/* 8 bit, bank valid */
286#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
287
288/*
289 * BR1/OR1 - SDRAM
290 *
291 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
292 */
293#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
294#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
295#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
296
297#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
298
299#define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
300#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
301
302/*
303 * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
304 */
305#define HPRO2_BASE 0xE0000000
306#define HPRO2_OR_AM 0xFFFF8000
307#define HPRO2_TIMING 0x00000934
308
309#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
310#define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
311
312/*
313 * BR3/OR3: not used
314 * BR4/OR4: not used
315 * BR5/OR5: not used
316 * BR6/OR6: not used
317 * BR7/OR7: not used
318 */
319
320/*
321 * MAMR settings for SDRAM
322 */
323
324/* periodic timer for refresh */
325#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
326
327/* 8 column SDRAM */
328#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
329 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
330 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
331/* 9 column SDRAM */
332#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
333 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
334 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
335
336/*
337 * Internal Definitions
338 *
339 * Boot Flags
340 */
341#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
342#define BOOTFLAG_WARM 0x02 /* Software reboot */
343
344#endif /* __CONFIG_H */