Aneesh V | 2ae610f | 2011-07-21 09:10:09 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * EMIF programming |
| 3 | * |
| 4 | * (C) Copyright 2010 |
| 5 | * Texas Instruments, <www.ti.com> |
| 6 | * |
| 7 | * Aneesh V <aneesh@ti.com> |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | #include <asm/arch/emif.h> |
| 30 | #include <asm/arch/clocks.h> |
| 31 | #include <asm/arch/sys_proto.h> |
| 32 | #include <asm/omap_common.h> |
| 33 | #include <asm/utils.h> |
| 34 | |
| 35 | static inline u32 emif_num(u32 base) |
| 36 | { |
| 37 | if (base == OMAP44XX_EMIF1) |
| 38 | return 1; |
| 39 | else if (base == OMAP44XX_EMIF2) |
| 40 | return 2; |
| 41 | else |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) |
| 46 | { |
| 47 | u32 mr; |
| 48 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 49 | |
| 50 | mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; |
| 51 | writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
| 52 | if (omap_revision() == OMAP4430_ES2_0) |
| 53 | mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); |
| 54 | else |
| 55 | mr = readl(&emif->emif_lpddr2_mode_reg_data); |
| 56 | debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), |
| 57 | cs, mr_addr, mr); |
| 58 | return mr; |
| 59 | } |
| 60 | |
| 61 | static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) |
| 62 | { |
| 63 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 64 | |
| 65 | mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; |
| 66 | writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
| 67 | writel(mr_val, &emif->emif_lpddr2_mode_reg_data); |
| 68 | } |
| 69 | |
| 70 | void emif_reset_phy(u32 base) |
| 71 | { |
| 72 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 73 | u32 iodft; |
| 74 | |
| 75 | iodft = readl(&emif->emif_iodft_tlgc); |
| 76 | iodft |= OMAP44XX_REG_RESET_PHY_MASK; |
| 77 | writel(iodft, &emif->emif_iodft_tlgc); |
| 78 | } |
| 79 | |
| 80 | static void do_lpddr2_init(u32 base, u32 cs) |
| 81 | { |
| 82 | u32 mr_addr; |
| 83 | |
| 84 | /* Wait till device auto initialization is complete */ |
| 85 | while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) |
| 86 | ; |
| 87 | set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); |
| 88 | /* |
| 89 | * tZQINIT = 1 us |
| 90 | * Enough loops assuming a maximum of 2GHz |
| 91 | */ |
| 92 | sdelay(2000); |
| 93 | set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); |
| 94 | set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); |
| 95 | /* |
| 96 | * Enable refresh along with writing MR2 |
| 97 | * Encoding of RL in MR2 is (RL - 2) |
| 98 | */ |
| 99 | mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK; |
| 100 | set_mr(base, cs, mr_addr, RL_FINAL - 2); |
| 101 | } |
| 102 | |
| 103 | static void lpddr2_init(u32 base, const struct emif_regs *regs) |
| 104 | { |
| 105 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 106 | |
| 107 | /* Not NVM */ |
| 108 | clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK); |
| 109 | |
| 110 | /* |
| 111 | * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM |
| 112 | * when EMIF_SDRAM_CONFIG register is written |
| 113 | */ |
| 114 | setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); |
| 115 | |
| 116 | /* |
| 117 | * Set the SDRAM_CONFIG and PHY_CTRL for the |
| 118 | * un-locked frequency & default RL |
| 119 | */ |
| 120 | writel(regs->sdram_config_init, &emif->emif_sdram_config); |
| 121 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
| 122 | |
| 123 | do_lpddr2_init(base, CS0); |
| 124 | if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK) |
| 125 | do_lpddr2_init(base, CS1); |
| 126 | |
| 127 | writel(regs->sdram_config, &emif->emif_sdram_config); |
| 128 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); |
| 129 | |
| 130 | /* Enable refresh now */ |
| 131 | clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); |
| 132 | |
| 133 | } |
| 134 | |
| 135 | static void emif_update_timings(u32 base, const struct emif_regs *regs) |
| 136 | { |
| 137 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 138 | |
| 139 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); |
| 140 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); |
| 141 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); |
| 142 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); |
| 143 | if (omap_revision() == OMAP4430_ES1_0) { |
| 144 | /* ES1 bug EMIF should be in force idle during freq_update */ |
| 145 | writel(0, &emif->emif_pwr_mgmt_ctrl); |
| 146 | } else { |
| 147 | writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); |
| 148 | writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); |
| 149 | } |
| 150 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); |
| 151 | writel(regs->zq_config, &emif->emif_zq_config); |
| 152 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); |
| 153 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); |
| 154 | /* |
| 155 | * Workaround: |
| 156 | * In a specific situation, the OCP interface between the DMM and |
| 157 | * EMIF may hang. |
| 158 | * 1. A TILER port is used to perform 2D burst writes of |
| 159 | * width 1 and height 8 |
| 160 | * 2. ELLAn port is used to perform reads |
| 161 | * 3. All accesses are routed to the same EMIF controller |
| 162 | * |
| 163 | * Work around to avoid this issue REG_SYS_THRESH_MAX value should |
| 164 | * be kept higher than default 0x7. As per recommondation 0x0A will |
| 165 | * be used for better performance with REG_LL_THRESH_MAX = 0x00 |
| 166 | */ |
| 167 | if (omap_revision() == OMAP4430_ES1_0) { |
| 168 | writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00, |
| 169 | &emif->emif_l3_config); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | static void do_sdram_init(u32 base) |
| 174 | { |
| 175 | const struct emif_regs *regs; |
| 176 | u32 in_sdram, emif_nr; |
| 177 | |
| 178 | debug(">>do_sdram_init() %x\n", base); |
| 179 | |
| 180 | in_sdram = running_from_sdram(); |
| 181 | emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; |
| 182 | |
| 183 | emif_get_reg_dump(emif_nr, ®s); |
| 184 | if (!regs) { |
| 185 | debug("EMIF: reg dump not provided\n"); |
| 186 | return; |
| 187 | } |
| 188 | |
| 189 | /* |
| 190 | * Initializing the LPDDR2 device can not happen from SDRAM. |
| 191 | * Changing the timing registers in EMIF can happen(going from one |
| 192 | * OPP to another) |
| 193 | */ |
| 194 | if (!in_sdram) |
| 195 | lpddr2_init(base, regs); |
| 196 | |
| 197 | /* Write to the shadow registers */ |
| 198 | emif_update_timings(base, regs); |
| 199 | |
| 200 | debug("<<do_sdram_init() %x\n", base); |
| 201 | } |
| 202 | |
| 203 | void sdram_init_pads(void) |
| 204 | { |
| 205 | u32 lpddr2io; |
| 206 | struct control_lpddr2io_regs *lpddr2io_regs = |
| 207 | (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; |
| 208 | u32 omap4_rev = omap_revision(); |
| 209 | |
| 210 | if (omap4_rev == OMAP4430_ES1_0) |
| 211 | lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; |
| 212 | else if (omap4_rev == OMAP4430_ES2_0) |
| 213 | lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; |
| 214 | else |
| 215 | return; /* Post ES2.1 reset values will work */ |
| 216 | |
| 217 | writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); |
| 218 | writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); |
| 219 | writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2); |
| 220 | writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); |
| 221 | writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); |
| 222 | writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2); |
| 223 | |
| 224 | writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2); |
| 225 | } |
| 226 | |
| 227 | static void emif_post_init_config(u32 base) |
| 228 | { |
| 229 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 230 | u32 omap4_rev = omap_revision(); |
| 231 | |
| 232 | /* reset phy on ES2.0 */ |
| 233 | if (omap4_rev == OMAP4430_ES2_0) |
| 234 | emif_reset_phy(base); |
| 235 | |
| 236 | /* Put EMIF back in smart idle on ES1.0 */ |
| 237 | if (omap4_rev == OMAP4430_ES1_0) |
| 238 | writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); |
| 239 | } |
| 240 | |
| 241 | static void dmm_init(u32 base) |
| 242 | { |
| 243 | const struct dmm_lisa_map_regs *lisa_map_regs; |
| 244 | |
| 245 | emif_get_dmm_regs(&lisa_map_regs); |
| 246 | |
| 247 | struct dmm_lisa_map_regs *hw_lisa_map_regs = |
| 248 | (struct dmm_lisa_map_regs *)base; |
| 249 | |
| 250 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); |
| 251 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); |
| 252 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); |
| 253 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); |
| 254 | |
| 255 | writel(lisa_map_regs->dmm_lisa_map_3, |
| 256 | &hw_lisa_map_regs->dmm_lisa_map_3); |
| 257 | writel(lisa_map_regs->dmm_lisa_map_2, |
| 258 | &hw_lisa_map_regs->dmm_lisa_map_2); |
| 259 | writel(lisa_map_regs->dmm_lisa_map_1, |
| 260 | &hw_lisa_map_regs->dmm_lisa_map_1); |
| 261 | writel(lisa_map_regs->dmm_lisa_map_0, |
| 262 | &hw_lisa_map_regs->dmm_lisa_map_0); |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * SDRAM initialization: |
| 267 | * SDRAM initialization has two parts: |
| 268 | * 1. Configuring the SDRAM device |
| 269 | * 2. Update the AC timings related parameters in the EMIF module |
| 270 | * (1) should be done only once and should not be done while we are |
| 271 | * running from SDRAM. |
| 272 | * (2) can and should be done more than once if OPP changes. |
| 273 | * Particularly, this may be needed when we boot without SPL and |
| 274 | * and using Configuration Header(CH). ROM code supports only at 50% OPP |
| 275 | * at boot (low power boot). So u-boot has to switch to OPP100 and update |
| 276 | * the frequency. So, |
| 277 | * Doing (1) and (2) makes sense - first time initialization |
| 278 | * Doing (2) and not (1) makes sense - OPP change (when using CH) |
| 279 | * Doing (1) and not (2) doen't make sense |
| 280 | * See do_sdram_init() for the details |
| 281 | */ |
| 282 | void sdram_init(void) |
| 283 | { |
| 284 | u32 in_sdram, size_prog, size_detect; |
| 285 | |
| 286 | debug(">>sdram_init()\n"); |
| 287 | |
| 288 | if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) |
| 289 | return; |
| 290 | |
| 291 | in_sdram = running_from_sdram(); |
| 292 | debug("in_sdram = %d\n", in_sdram); |
| 293 | |
| 294 | if (!in_sdram) { |
| 295 | sdram_init_pads(); |
| 296 | bypass_dpll(&prcm->cm_clkmode_dpll_core); |
| 297 | } |
| 298 | |
| 299 | do_sdram_init(OMAP44XX_EMIF1); |
| 300 | do_sdram_init(OMAP44XX_EMIF2); |
| 301 | |
| 302 | if (!in_sdram) { |
| 303 | dmm_init(OMAP44XX_DMM_LISA_MAP_BASE); |
| 304 | emif_post_init_config(OMAP44XX_EMIF1); |
| 305 | emif_post_init_config(OMAP44XX_EMIF2); |
| 306 | |
| 307 | } |
| 308 | |
| 309 | /* for the shadow registers to take effect */ |
| 310 | freq_update_core(); |
| 311 | |
| 312 | /* Do some testing after the init */ |
| 313 | if (!in_sdram) { |
| 314 | size_prog = omap4_sdram_size(); |
| 315 | size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
| 316 | size_prog); |
| 317 | /* Compare with the size programmed */ |
| 318 | if (size_detect != size_prog) { |
| 319 | printf("SDRAM: identified size not same as expected" |
| 320 | " size identified: %x expected: %x\n", |
| 321 | size_detect, |
| 322 | size_prog); |
| 323 | } else |
| 324 | debug("get_ram_size() successful"); |
| 325 | } |
| 326 | |
| 327 | debug("<<sdram_init()\n"); |
| 328 | } |