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Oliver Schinagl5c7f10f2013-07-26 12:56:58 +02001/*
Hans de Goedebdcdf842014-11-29 23:54:25 +01002 * AXP221 and AXP223 driver
3 *
4 * IMPORTANT when making changes to this file check that the registers
5 * used are the same for the axp221 and axp223.
6 *
7 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +02008 * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
14#include <errno.h>
15#include <asm/arch/p2wi.h>
Hans de Goedebdcdf842014-11-29 23:54:25 +010016#include <asm/arch/rsb.h>
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020017#include <axp221.h>
18
Hans de Goedebdcdf842014-11-29 23:54:25 +010019/*
20 * The axp221 uses the p2wi bus, the axp223 is identical (for all registers
21 * used sofar) but uses the rsb bus. These functions abstract this.
22 */
23static int pmic_bus_init(void)
24{
25#ifdef CONFIG_MACH_SUN6I
26 p2wi_init();
27 return p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
28 AXP221_INIT_DATA);
29#else
30 int ret;
31
32 rsb_init();
33
34 ret = rsb_set_device_mode(AXP223_DEVICE_MODE_DATA);
35 if (ret)
36 return ret;
37
38 return rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
39#endif
40}
41
42static int pmic_bus_read(const u8 addr, u8 *data)
43{
44#ifdef CONFIG_MACH_SUN6I
45 return p2wi_read(addr, data);
46#else
47 return rsb_read(AXP223_RUNTIME_ADDR, addr, data);
48#endif
49}
50
51static int pmic_bus_write(const u8 addr, u8 data)
52{
53#ifdef CONFIG_MACH_SUN6I
54 return p2wi_write(addr, data);
55#else
56 return rsb_write(AXP223_RUNTIME_ADDR, addr, data);
57#endif
58}
59
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020060static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
61{
62 if (mvolt < min)
63 mvolt = min;
64 else if (mvolt > max)
65 mvolt = max;
66
67 return (mvolt - min) / div;
68}
69
70static int axp221_setbits(u8 reg, u8 bits)
71{
72 int ret;
73 u8 val;
74
Hans de Goedebdcdf842014-11-29 23:54:25 +010075 ret = pmic_bus_read(reg, &val);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020076 if (ret)
77 return ret;
78
79 val |= bits;
Hans de Goedebdcdf842014-11-29 23:54:25 +010080 return pmic_bus_write(reg, val);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020081}
82
Hans de Goede50e0d5e2014-12-13 14:02:38 +010083static int axp221_clrbits(u8 reg, u8 bits)
84{
85 int ret;
86 u8 val;
87
88 ret = pmic_bus_read(reg, &val);
89 if (ret)
90 return ret;
91
92 val &= ~bits;
93 return pmic_bus_write(reg, val);
94}
95
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020096int axp221_set_dcdc1(unsigned int mvolt)
97{
98 int ret;
99 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
100
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100101 if (mvolt == 0)
102 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
103 AXP221_OUTPUT_CTRL1_DCDC1_EN);
104
Hans de Goedebdcdf842014-11-29 23:54:25 +0100105 ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200106 if (ret)
107 return ret;
108
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100109 ret = axp221_setbits(AXP221_OUTPUT_CTRL2,
110 AXP221_OUTPUT_CTRL2_DCDC1SW_EN);
111 if (ret)
112 return ret;
113
114 return axp221_setbits(AXP221_OUTPUT_CTRL1,
115 AXP221_OUTPUT_CTRL1_DCDC1_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200116}
117
118int axp221_set_dcdc2(unsigned int mvolt)
119{
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100120 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200121 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
122
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100123 if (mvolt == 0)
124 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
125 AXP221_OUTPUT_CTRL1_DCDC2_EN);
126
127 ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg);
128 if (ret)
129 return ret;
130
131 return axp221_setbits(AXP221_OUTPUT_CTRL1,
132 AXP221_OUTPUT_CTRL1_DCDC2_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200133}
134
135int axp221_set_dcdc3(unsigned int mvolt)
136{
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100137 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200138 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20);
139
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100140 if (mvolt == 0)
141 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
142 AXP221_OUTPUT_CTRL1_DCDC3_EN);
143
144 ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg);
145 if (ret)
146 return ret;
147
148 return axp221_setbits(AXP221_OUTPUT_CTRL1,
149 AXP221_OUTPUT_CTRL1_DCDC3_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200150}
151
152int axp221_set_dcdc4(unsigned int mvolt)
153{
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100154 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200155 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
156
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100157 if (mvolt == 0)
158 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
159 AXP221_OUTPUT_CTRL1_DCDC4_EN);
160
161 ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg);
162 if (ret)
163 return ret;
164
165 return axp221_setbits(AXP221_OUTPUT_CTRL1,
166 AXP221_OUTPUT_CTRL1_DCDC4_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200167}
168
169int axp221_set_dcdc5(unsigned int mvolt)
170{
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100171 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200172 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50);
173
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100174 if (mvolt == 0)
175 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
176 AXP221_OUTPUT_CTRL1_DCDC5_EN);
177
178 ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg);
179 if (ret)
180 return ret;
181
182 return axp221_setbits(AXP221_OUTPUT_CTRL1,
183 AXP221_OUTPUT_CTRL1_DCDC5_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200184}
185
186int axp221_set_dldo1(unsigned int mvolt)
187{
188 int ret;
189 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
190
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100191 if (mvolt == 0)
192 return axp221_clrbits(AXP221_OUTPUT_CTRL2,
193 AXP221_OUTPUT_CTRL2_DLDO1_EN);
194
Hans de Goedebdcdf842014-11-29 23:54:25 +0100195 ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200196 if (ret)
197 return ret;
198
199 return axp221_setbits(AXP221_OUTPUT_CTRL2,
200 AXP221_OUTPUT_CTRL2_DLDO1_EN);
201}
202
203int axp221_set_dldo2(unsigned int mvolt)
204{
205 int ret;
206 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
207
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100208 if (mvolt == 0)
209 return axp221_clrbits(AXP221_OUTPUT_CTRL2,
210 AXP221_OUTPUT_CTRL2_DLDO2_EN);
211
Hans de Goedebdcdf842014-11-29 23:54:25 +0100212 ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200213 if (ret)
214 return ret;
215
216 return axp221_setbits(AXP221_OUTPUT_CTRL2,
217 AXP221_OUTPUT_CTRL2_DLDO2_EN);
218}
219
220int axp221_set_dldo3(unsigned int mvolt)
221{
222 int ret;
223 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
224
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100225 if (mvolt == 0)
226 return axp221_clrbits(AXP221_OUTPUT_CTRL2,
227 AXP221_OUTPUT_CTRL2_DLDO3_EN);
228
Hans de Goedebdcdf842014-11-29 23:54:25 +0100229 ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200230 if (ret)
231 return ret;
232
233 return axp221_setbits(AXP221_OUTPUT_CTRL2,
234 AXP221_OUTPUT_CTRL2_DLDO3_EN);
235}
236
237int axp221_set_dldo4(unsigned int mvolt)
238{
239 int ret;
240 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
241
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100242 if (mvolt == 0)
243 return axp221_clrbits(AXP221_OUTPUT_CTRL2,
244 AXP221_OUTPUT_CTRL2_DLDO4_EN);
245
Hans de Goedebdcdf842014-11-29 23:54:25 +0100246 ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200247 if (ret)
248 return ret;
249
250 return axp221_setbits(AXP221_OUTPUT_CTRL2,
251 AXP221_OUTPUT_CTRL2_DLDO4_EN);
252}
253
254int axp221_set_aldo1(unsigned int mvolt)
255{
256 int ret;
257 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
258
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100259 if (mvolt == 0)
260 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
261 AXP221_OUTPUT_CTRL1_ALDO1_EN);
262
Hans de Goedebdcdf842014-11-29 23:54:25 +0100263 ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200264 if (ret)
265 return ret;
266
267 return axp221_setbits(AXP221_OUTPUT_CTRL1,
268 AXP221_OUTPUT_CTRL1_ALDO1_EN);
269}
270
271int axp221_set_aldo2(unsigned int mvolt)
272{
273 int ret;
274 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
275
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100276 if (mvolt == 0)
277 return axp221_clrbits(AXP221_OUTPUT_CTRL1,
278 AXP221_OUTPUT_CTRL1_ALDO2_EN);
279
Hans de Goedebdcdf842014-11-29 23:54:25 +0100280 ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200281 if (ret)
282 return ret;
283
284 return axp221_setbits(AXP221_OUTPUT_CTRL1,
285 AXP221_OUTPUT_CTRL1_ALDO2_EN);
286}
287
288int axp221_set_aldo3(unsigned int mvolt)
289{
290 int ret;
291 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
292
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100293 if (mvolt == 0)
294 return axp221_clrbits(AXP221_OUTPUT_CTRL3,
295 AXP221_OUTPUT_CTRL3_ALDO3_EN);
296
Hans de Goedebdcdf842014-11-29 23:54:25 +0100297 ret = pmic_bus_write(AXP221_ALDO3_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200298 if (ret)
299 return ret;
300
301 return axp221_setbits(AXP221_OUTPUT_CTRL3,
302 AXP221_OUTPUT_CTRL3_ALDO3_EN);
303}
304
305int axp221_init(void)
306{
Hans de Goede3c781192015-01-11 19:43:56 +0100307 /* This cannot be 0 because it is used in SPL before BSS is ready */
308 static int needs_init = 1;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200309 u8 axp_chip_id;
310 int ret;
311
Hans de Goede3c781192015-01-11 19:43:56 +0100312 if (!needs_init)
313 return 0;
314
Hans de Goedebdcdf842014-11-29 23:54:25 +0100315 ret = pmic_bus_init();
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200316 if (ret)
317 return ret;
318
Hans de Goedebdcdf842014-11-29 23:54:25 +0100319 ret = pmic_bus_read(AXP221_CHIP_ID, &axp_chip_id);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200320 if (ret)
321 return ret;
322
323 if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
324 return -ENODEV;
325
Hans de Goede3c781192015-01-11 19:43:56 +0100326 needs_init = 0;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200327 return 0;
328}
Hans de Goedef3fba562014-11-25 16:37:52 +0100329
330int axp221_get_sid(unsigned int *sid)
331{
332 u8 *dest = (u8 *)sid;
333 int i, ret;
334
335 ret = axp221_init();
336 if (ret)
337 return ret;
338
Hans de Goedebdcdf842014-11-29 23:54:25 +0100339 ret = pmic_bus_write(AXP221_PAGE, 1);
Hans de Goedef3fba562014-11-25 16:37:52 +0100340 if (ret)
341 return ret;
342
343 for (i = 0; i < 16; i++) {
Hans de Goedebdcdf842014-11-29 23:54:25 +0100344 ret = pmic_bus_read(AXP221_SID + i, &dest[i]);
Hans de Goedef3fba562014-11-25 16:37:52 +0100345 if (ret)
346 return ret;
347 }
348
Hans de Goedebdcdf842014-11-29 23:54:25 +0100349 pmic_bus_write(AXP221_PAGE, 0);
Hans de Goedef3fba562014-11-25 16:37:52 +0100350
351 for (i = 0; i < 4; i++)
352 sid[i] = be32_to_cpu(sid[i]);
353
354 return 0;
355}
Hans de Goede2abac622015-01-11 19:58:03 +0100356
357static int axp_drivebus_setup(void)
358{
359 int ret;
360
361 ret = axp221_init();
362 if (ret)
363 return ret;
364
365 /* Set N_VBUSEN pin to output / DRIVEBUS function */
366 return axp221_clrbits(AXP221_MISC_CTRL, AXP221_MISC_CTRL_N_VBUSEN_FUNC);
367}
368
369int axp_drivebus_enable(void)
370{
371 int ret;
372
373 ret = axp_drivebus_setup();
374 if (ret)
375 return ret;
376
377 /* Set DRIVEBUS high */
378 return axp221_setbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS);
379}
380
381int axp_drivebus_disable(void)
382{
383 int ret;
384
385 ret = axp_drivebus_setup();
386 if (ret)
387 return ret;
388
389 /* Set DRIVEBUS low */
390 return axp221_clrbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS);
391}