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wdenk652a10c2005-01-09 23:48:14 +00001/*
2 * (C) Copyright 2001
3 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk652a10c2005-01-09 23:48:14 +00005 */
6
7/*
8 * board/config.h - configuration options, board specific
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenk652a10c2005-01-09 23:48:14 +000020#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
21
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
23
wdenk652a10c2005-01-09 23:48:14 +000024#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
25#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
26
27#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
28
29#define CONFIG_BAUDRATE 9600
30
31#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
32
33#define CONFIG_RAMBOOT \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010034 "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
35 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk652a10c2005-01-09 23:48:14 +000036 "bootm ffc00000 ffca0000"
37#define CONFIG_NFSBOOT \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010038 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
39 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk652a10c2005-01-09 23:48:14 +000040 "bootm ffc00000"
41
42#undef CONFIG_BOOTARGS
Wolfgang Denkfe126d82005-11-20 21:40:11 +010043#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
wdenk652a10c2005-01-09 23:48:14 +000044
45
Ben Warren96e21f82008-10-27 23:50:15 -070046#define CONFIG_PPC4xx_EMAC
wdenk652a10c2005-01-09 23:48:14 +000047#define CONFIG_MII 1 /* MII PHY management */
48#define CONFIG_PHY_ADDR 0 /* PHY address */
49#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
50
51#define CONFIG_EXTRA_ENV_SETTINGS \
52 "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
53 "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
54 "f=0x08 tn=sbc405 o=emac \0" \
55 "env_startaddr=FF000000\0" \
56 "env_endaddr=FF03FFFF\0" \
57 "loadfile=vxWorks.st\0" \
58 "loadaddr=0x01000000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
wdenk652a10c2005-01-09 23:48:14 +000060 "uboot_startaddr=FFFC0000\0" \
61 "uboot_endaddr=FFFFFFFF\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "update=tftp ${loadaddr} u-boot.bin;" \
63 "protect off ${uboot_startaddr} ${uboot_endaddr};" \
64 "era ${uboot_startaddr} ${uboot_endaddr};" \
65 "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
66 "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
67 "zapenv=protect off ${env_startaddr} ${env_endaddr};" \
68 "era ${env_startaddr} ${env_endaddr};" \
69 "protect on ${env_startaddr} ${env_endaddr}\0"
wdenk652a10c2005-01-09 23:48:14 +000070
71#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
72
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050073/*
74 * BOOTP options
75 */
76#define CONFIG_BOOTP_SUBNETMASK
77#define CONFIG_BOOTP_GATEWAY
78#define CONFIG_BOOTP_HOSTNAME
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_BOOTFILESIZE
81
wdenk652a10c2005-01-09 23:48:14 +000082
83#define CONFIG_ENV_OVERWRITE
84
wdenk652a10c2005-01-09 23:48:14 +000085
Jon Loeliger866e3082007-07-04 22:30:58 -050086/*
87 * Command line configuration.
88 */
89#include <config_cmd_default.h>
90
91#define CONFIG_CMD_BSP
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_IRQ
95#define CONFIG_CMD_MII
96#define CONFIG_CMD_PCI
97#define CONFIG_CMD_PING
98#define CONFIG_CMD_SDRAM
99
wdenk652a10c2005-01-09 23:48:14 +0000100
101#undef CONFIG_WATCHDOG /* watchdog disabled */
102
103#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
104
wdenk652a10c2005-01-09 23:48:14 +0000105#define CONFIG_IPADDR 192.168.193.102
106#define CONFIG_NETMASK 255.255.255.224
107#define CONFIG_SERVERIP 192.168.193.119
108#define CONFIG_GATEWAYIP 192.168.193.97
109
110/*
111 * Miscellaneous configurable options
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk652a10c2005-01-09 23:48:14 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenk652a10c2005-01-09 23:48:14 +0000116
Jon Loeliger866e3082007-07-04 22:30:58 -0500117#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk652a10c2005-01-09 23:48:14 +0000119#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk652a10c2005-01-09 23:48:14 +0000121#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
123#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
124#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk652a10c2005-01-09 23:48:14 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
127#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk652a10c2005-01-09 23:48:14 +0000128
Stefan Roese550650d2010-09-20 16:05:31 +0200129#define CONFIG_CONS_INDEX 1 /* Use UART0 */
130#define CONFIG_SYS_NS16550
131#define CONFIG_SYS_NS16550_SERIAL
132#define CONFIG_SYS_NS16550_REG_SIZE 1
133#define CONFIG_SYS_NS16550_CLK get_serial_clock()
134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_BASE_BAUD 691200
wdenk652a10c2005-01-09 23:48:14 +0000137
138/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk652a10c2005-01-09 23:48:14 +0000140 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
141 57600, 115200, 230400, 460800, 921600 }
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
144#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
wdenk652a10c2005-01-09 23:48:14 +0000145
wdenk652a10c2005-01-09 23:48:14 +0000146#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
wdenk652a10c2005-01-09 23:48:14 +0000149
Dirk Eibach880540d2013-04-25 02:40:01 +0000150#define CONFIG_SYS_I2C
151#define CONFIG_SYS_I2C_PPC4XX
152#define CONFIG_SYS_I2C_PPC4XX_CH0
153#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
154#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenk652a10c2005-01-09 23:48:14 +0000155
156/*-----------------------------------------------------------------------
157 * PCI stuff
158 *-----------------------------------------------------------------------
159 */
160#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
161#define PCI_HOST_FORCE 1 /* configure as pci host */
162#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
163
164#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000165#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk652a10c2005-01-09 23:48:14 +0000166#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
167#define CONFIG_PCI_PNP /* do pci plug-and-play */
168 /* resource configuration */
169
170#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
173#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
174#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
175#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
176#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
177#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
178#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
179#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
180#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk652a10c2005-01-09 23:48:14 +0000181
182/*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration
184 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk652a10c2005-01-09 23:48:14 +0000186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SDRAM_BASE 0x00000000
188#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
189#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
190#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenk652a10c2005-01-09 23:48:14 +0000191
192/*
193 * For booting Linux, the board info and command line data
194 * have to be in the first 8 MB of memory, since this is
195 * the maximum mapped by the Linux kernel during initialization.
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk652a10c2005-01-09 23:48:14 +0000198
199/*-----------------------------------------------------------------------
200 * FLASH organization
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_BASE 0xFF000000
203#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
204#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
205#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
206#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
207#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
208#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
209#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
210#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
211#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenk652a10c2005-01-09 23:48:14 +0000212
213/*-----------------------------------------------------------------------
214 * Environment Variable setup
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200217#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
219#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
220#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenk652a10c2005-01-09 23:48:14 +0000221
222/*-----------------------------------------------------------------------
wdenk652a10c2005-01-09 23:48:14 +0000223 * External Bus Controller (EBC) Setup
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */
wdenk652a10c2005-01-09 23:48:14 +0000226
227/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_EBC_PB0AP 0x92015480
229#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
wdenk652a10c2005-01-09 23:48:14 +0000230
231/*-----------------------------------------------------------------------
232 * Definitions for initial stack pointer and data area (in data cache)
233 */
234
235/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenk652a10c2005-01-09 23:48:14 +0000237
238/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
240#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenk652a10c2005-01-09 23:48:14 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200243#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200244#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk652a10c2005-01-09 23:48:14 +0000246
247/*-----------------------------------------------------------------------
248 * Definitions for Serial Presence Detect EEPROM address
249 * (to get SDRAM settings)
250 */
251#define SPD_EEPROM_ADDRESS 0x50
252#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
253
wdenk652a10c2005-01-09 23:48:14 +0000254#endif /* __CONFIG_H */