blob: 98bd5dfc70f237942f2d8d1d7d5fccc58b2ea592 [file] [log] [blame]
Vikas Manocha0a836ce2015-05-03 14:10:34 -07001/dts-v1/;
2
3/ {
4 model = "ST STV0991 application board";
5 compatible = "st,stv0991";
6 #address-cells = <1>;
7 #size-cells = <1>;
8
9 chosen {
10 stdout-path = &uart0;
11 };
12
13 memory {
14 device_type="memory";
15 reg = <0x0 0x198000>;
16 };
17
18 uart0: serial@0x80406000 {
19 compatible = "arm,pl011", "arm,primecell";
20 reg = <0x80406000 0x1000>;
21 clock = <2700000>;
22 };
Vikas Manocha51d55832015-07-02 18:29:42 -070023
24 aliases {
25 spi0 = "/spi@80203000"; /* QSPI */
26 };
27
28 qspi: spi@80203000 {
Simon Goldschmidt2a3a9992018-11-02 11:54:51 +010029 compatible = "cdns,qspi-nor";
Vikas Manocha51d55832015-07-02 18:29:42 -070030 #address-cells = <1>;
31 #size-cells = <0>;
32 reg = <0x80203000 0x100>,
33 <0x40000000 0x1000000>;
34 clocks = <3750000>;
Jason Rush6e62b172018-01-23 17:13:10 -060035 cdns,fifo-depth = <256>;
36 cdns,fifo-width = <4>;
37 cdns,trigger-address = <0x40000000>;
Vikas Manocha51d55832015-07-02 18:29:42 -070038 status = "okay";
39
40 flash0: n25q32@0 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "spi-flash";
44 reg = <0>; /* chip select */
45 spi-max-frequency = <50000000>;
46 m25p,fast-read;
47 page-size = <256>;
48 block-size = <16>; /* 2^16, 64KB */
Jason Rush6e62b172018-01-23 17:13:10 -060049 cdns,tshsl-ns = <50>;
50 cdns,tsd2d-ns = <50>;
51 cdns,tchsh-ns = <4>;
52 cdns,tslch-ns = <4>;
Vikas Manocha51d55832015-07-02 18:29:42 -070053 };
54 };
Vikas Manocha0a836ce2015-05-03 14:10:34 -070055};