blob: 9d8c4ebd15a82069f68953c85061d8df2d59e1c7 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese51c580c2014-11-07 14:10:41 +01002/*
3 * Copyright (C) 2012 Altera <www.altera.com>
Stefan Roese51c580c2014-11-07 14:10:41 +01004 */
5
6#include "skeleton.dtsi"
7#include <dt-bindings/reset/altr,rst-mgr.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 aliases {
14 ethernet0 = &gmac0;
15 ethernet1 = &gmac1;
Dinh Nguyen67e44362018-04-04 17:18:22 -050016 i2c0 = &i2c0;
17 i2c1 = &i2c1;
18 i2c2 = &i2c2;
19 i2c3 = &i2c3;
Stefan Roese51c580c2014-11-07 14:10:41 +010020 serial0 = &uart0;
21 serial1 = &uart1;
22 timer0 = &timer0;
23 timer1 = &timer1;
24 timer2 = &timer2;
25 timer3 = &timer3;
Marek Vasutb09b72d2015-07-21 11:25:14 +020026 spi0 = &qspi;
27 spi1 = &spi0;
28 spi2 = &spi1;
Stefan Roese51c580c2014-11-07 14:10:41 +010029 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 };
47 };
48
49 intc: intc@fffed000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
55 };
56
57 soc {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 device_type = "soc";
62 interrupt-parent = <&intc>;
63 ranges;
64
65 amba {
66 compatible = "arm,amba-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
71 pdma: pdma@ffe01000 {
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
75 <0 105 4>,
76 <0 106 4>,
77 <0 107 4>,
78 <0 108 4>,
79 <0 109 4>,
80 <0 110 4>,
81 <0 111 4>;
82 #dma-cells = <1>;
83 #dma-channels = <8>;
84 #dma-requests = <32>;
85 clocks = <&l4_main_clk>;
86 clock-names = "apb_pclk";
87 };
88 };
89
90 can0: can@ffc00000 {
91 compatible = "bosch,d_can";
92 reg = <0xffc00000 0x1000>;
93 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
94 clocks = <&can0_clk>;
95 status = "disabled";
96 };
97
98 can1: can@ffc01000 {
99 compatible = "bosch,d_can";
100 reg = <0xffc01000 0x1000>;
101 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
102 clocks = <&can1_clk>;
103 status = "disabled";
104 };
105
106 clkmgr@ffd04000 {
107 compatible = "altr,clk-mgr";
108 reg = <0xffd04000 0x1000>;
109
110 clocks {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 osc1: osc1 {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 };
118
119 osc2: osc2 {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 };
123
124 f2s_periph_ref_clk: f2s_periph_ref_clk {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 };
128
129 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 };
133
134 main_pll: main_pll {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 #clock-cells = <0>;
138 compatible = "altr,socfpga-pll-clock";
139 clocks = <&osc1>;
140 reg = <0x40>;
141
142 mpuclk: mpuclk {
143 #clock-cells = <0>;
144 compatible = "altr,socfpga-perip-clk";
145 clocks = <&main_pll>;
146 div-reg = <0xe0 0 9>;
147 reg = <0x48>;
148 };
149
150 mainclk: mainclk {
151 #clock-cells = <0>;
152 compatible = "altr,socfpga-perip-clk";
153 clocks = <&main_pll>;
154 div-reg = <0xe4 0 9>;
155 reg = <0x4C>;
156 };
157
158 dbg_base_clk: dbg_base_clk {
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-perip-clk";
161 clocks = <&main_pll>;
162 div-reg = <0xe8 0 9>;
163 reg = <0x50>;
164 };
165
166 main_qspi_clk: main_qspi_clk {
167 #clock-cells = <0>;
168 compatible = "altr,socfpga-perip-clk";
169 clocks = <&main_pll>;
170 reg = <0x54>;
171 };
172
173 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
174 #clock-cells = <0>;
175 compatible = "altr,socfpga-perip-clk";
176 clocks = <&main_pll>;
177 reg = <0x58>;
178 };
179
180 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x5C>;
185 };
186 };
187
188 periph_pll: periph_pll {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 #clock-cells = <0>;
192 compatible = "altr,socfpga-pll-clock";
193 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
194 reg = <0x80>;
195
196 emac0_clk: emac0_clk {
197 #clock-cells = <0>;
198 compatible = "altr,socfpga-perip-clk";
199 clocks = <&periph_pll>;
200 reg = <0x88>;
201 };
202
203 emac1_clk: emac1_clk {
204 #clock-cells = <0>;
205 compatible = "altr,socfpga-perip-clk";
206 clocks = <&periph_pll>;
207 reg = <0x8C>;
208 };
209
210 per_qspi_clk: per_qsi_clk {
211 #clock-cells = <0>;
212 compatible = "altr,socfpga-perip-clk";
213 clocks = <&periph_pll>;
214 reg = <0x90>;
215 };
216
217 per_nand_mmc_clk: per_nand_mmc_clk {
218 #clock-cells = <0>;
219 compatible = "altr,socfpga-perip-clk";
220 clocks = <&periph_pll>;
221 reg = <0x94>;
222 };
223
224 per_base_clk: per_base_clk {
225 #clock-cells = <0>;
226 compatible = "altr,socfpga-perip-clk";
227 clocks = <&periph_pll>;
228 reg = <0x98>;
229 };
230
231 h2f_usr1_clk: h2f_usr1_clk {
232 #clock-cells = <0>;
233 compatible = "altr,socfpga-perip-clk";
234 clocks = <&periph_pll>;
235 reg = <0x9C>;
236 };
237 };
238
239 sdram_pll: sdram_pll {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 #clock-cells = <0>;
243 compatible = "altr,socfpga-pll-clock";
244 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
245 reg = <0xC0>;
246
247 ddr_dqs_clk: ddr_dqs_clk {
248 #clock-cells = <0>;
249 compatible = "altr,socfpga-perip-clk";
250 clocks = <&sdram_pll>;
251 reg = <0xC8>;
252 };
253
254 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
255 #clock-cells = <0>;
256 compatible = "altr,socfpga-perip-clk";
257 clocks = <&sdram_pll>;
258 reg = <0xCC>;
259 };
260
261 ddr_dq_clk: ddr_dq_clk {
262 #clock-cells = <0>;
263 compatible = "altr,socfpga-perip-clk";
264 clocks = <&sdram_pll>;
265 reg = <0xD0>;
266 };
267
268 h2f_usr2_clk: h2f_usr2_clk {
269 #clock-cells = <0>;
270 compatible = "altr,socfpga-perip-clk";
271 clocks = <&sdram_pll>;
272 reg = <0xD4>;
273 };
274 };
275
276 mpu_periph_clk: mpu_periph_clk {
277 #clock-cells = <0>;
278 compatible = "altr,socfpga-perip-clk";
279 clocks = <&mpuclk>;
280 fixed-divider = <4>;
281 };
282
283 mpu_l2_ram_clk: mpu_l2_ram_clk {
284 #clock-cells = <0>;
285 compatible = "altr,socfpga-perip-clk";
286 clocks = <&mpuclk>;
287 fixed-divider = <2>;
288 };
289
290 l4_main_clk: l4_main_clk {
291 #clock-cells = <0>;
292 compatible = "altr,socfpga-gate-clk";
293 clocks = <&mainclk>;
294 clk-gate = <0x60 0>;
295 };
296
297 l3_main_clk: l3_main_clk {
298 #clock-cells = <0>;
299 compatible = "altr,socfpga-perip-clk";
300 clocks = <&mainclk>;
301 fixed-divider = <1>;
302 };
303
304 l3_mp_clk: l3_mp_clk {
305 #clock-cells = <0>;
306 compatible = "altr,socfpga-gate-clk";
307 clocks = <&mainclk>;
308 div-reg = <0x64 0 2>;
309 clk-gate = <0x60 1>;
310 };
311
312 l3_sp_clk: l3_sp_clk {
313 #clock-cells = <0>;
314 compatible = "altr,socfpga-gate-clk";
315 clocks = <&mainclk>;
316 div-reg = <0x64 2 2>;
317 };
318
319 l4_mp_clk: l4_mp_clk {
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-gate-clk";
322 clocks = <&mainclk>, <&per_base_clk>;
323 div-reg = <0x64 4 3>;
324 clk-gate = <0x60 2>;
325 };
326
327 l4_sp_clk: l4_sp_clk {
328 #clock-cells = <0>;
329 compatible = "altr,socfpga-gate-clk";
330 clocks = <&mainclk>, <&per_base_clk>;
331 div-reg = <0x64 7 3>;
332 clk-gate = <0x60 3>;
333 };
334
335 dbg_at_clk: dbg_at_clk {
336 #clock-cells = <0>;
337 compatible = "altr,socfpga-gate-clk";
338 clocks = <&dbg_base_clk>;
339 div-reg = <0x68 0 2>;
340 clk-gate = <0x60 4>;
341 };
342
343 dbg_clk: dbg_clk {
344 #clock-cells = <0>;
345 compatible = "altr,socfpga-gate-clk";
346 clocks = <&dbg_base_clk>;
347 div-reg = <0x68 2 2>;
348 clk-gate = <0x60 5>;
349 };
350
351 dbg_trace_clk: dbg_trace_clk {
352 #clock-cells = <0>;
353 compatible = "altr,socfpga-gate-clk";
354 clocks = <&dbg_base_clk>;
355 div-reg = <0x6C 0 3>;
356 clk-gate = <0x60 6>;
357 };
358
359 dbg_timer_clk: dbg_timer_clk {
360 #clock-cells = <0>;
361 compatible = "altr,socfpga-gate-clk";
362 clocks = <&dbg_base_clk>;
363 clk-gate = <0x60 7>;
364 };
365
366 cfg_clk: cfg_clk {
367 #clock-cells = <0>;
368 compatible = "altr,socfpga-gate-clk";
369 clocks = <&cfg_h2f_usr0_clk>;
370 clk-gate = <0x60 8>;
371 };
372
373 h2f_user0_clk: h2f_user0_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-gate-clk";
376 clocks = <&cfg_h2f_usr0_clk>;
377 clk-gate = <0x60 9>;
378 };
379
380 emac_0_clk: emac_0_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-gate-clk";
383 clocks = <&emac0_clk>;
384 clk-gate = <0xa0 0>;
385 };
386
387 emac_1_clk: emac_1_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-gate-clk";
390 clocks = <&emac1_clk>;
391 clk-gate = <0xa0 1>;
392 };
393
394 usb_mp_clk: usb_mp_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-gate-clk";
397 clocks = <&per_base_clk>;
398 clk-gate = <0xa0 2>;
399 div-reg = <0xa4 0 3>;
400 };
401
402 spi_m_clk: spi_m_clk {
403 #clock-cells = <0>;
404 compatible = "altr,socfpga-gate-clk";
405 clocks = <&per_base_clk>;
406 clk-gate = <0xa0 3>;
407 div-reg = <0xa4 3 3>;
408 };
409
410 can0_clk: can0_clk {
411 #clock-cells = <0>;
412 compatible = "altr,socfpga-gate-clk";
413 clocks = <&per_base_clk>;
414 clk-gate = <0xa0 4>;
415 div-reg = <0xa4 6 3>;
416 };
417
418 can1_clk: can1_clk {
419 #clock-cells = <0>;
420 compatible = "altr,socfpga-gate-clk";
421 clocks = <&per_base_clk>;
422 clk-gate = <0xa0 5>;
423 div-reg = <0xa4 9 3>;
424 };
425
426 gpio_db_clk: gpio_db_clk {
427 #clock-cells = <0>;
428 compatible = "altr,socfpga-gate-clk";
429 clocks = <&per_base_clk>;
430 clk-gate = <0xa0 6>;
431 div-reg = <0xa8 0 24>;
432 };
433
434 h2f_user1_clk: h2f_user1_clk {
435 #clock-cells = <0>;
436 compatible = "altr,socfpga-gate-clk";
437 clocks = <&h2f_usr1_clk>;
438 clk-gate = <0xa0 7>;
439 };
440
441 sdmmc_clk: sdmmc_clk {
442 #clock-cells = <0>;
443 compatible = "altr,socfpga-gate-clk";
444 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
445 clk-gate = <0xa0 8>;
446 clk-phase = <0 135>;
447 };
448
449 nand_x_clk: nand_x_clk {
450 #clock-cells = <0>;
451 compatible = "altr,socfpga-gate-clk";
452 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
453 clk-gate = <0xa0 9>;
454 };
455
456 nand_clk: nand_clk {
457 #clock-cells = <0>;
458 compatible = "altr,socfpga-gate-clk";
459 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
460 clk-gate = <0xa0 10>;
461 fixed-divider = <4>;
462 };
463
464 qspi_clk: qspi_clk {
465 #clock-cells = <0>;
466 compatible = "altr,socfpga-gate-clk";
467 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
468 clk-gate = <0xa0 11>;
469 };
470 };
471 };
472
473 gmac0: ethernet@ff700000 {
474 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
475 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
476 reg = <0xff700000 0x2000>;
477 interrupts = <0 115 4>;
478 interrupt-names = "macirq";
479 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
480 clocks = <&emac0_clk>;
481 clock-names = "stmmaceth";
482 resets = <&rst EMAC0_RESET>;
483 reset-names = "stmmaceth";
484 snps,multicast-filter-bins = <256>;
485 snps,perfect-filter-entries = <128>;
486 status = "disabled";
487 };
488
489 gmac1: ethernet@ff702000 {
490 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
491 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
492 reg = <0xff702000 0x2000>;
493 interrupts = <0 120 4>;
494 interrupt-names = "macirq";
495 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
496 clocks = <&emac1_clk>;
497 clock-names = "stmmaceth";
498 resets = <&rst EMAC1_RESET>;
499 reset-names = "stmmaceth";
500 snps,multicast-filter-bins = <256>;
501 snps,perfect-filter-entries = <128>;
502 status = "disabled";
503 };
504
505 i2c0: i2c@ffc04000 {
506 #address-cells = <1>;
507 #size-cells = <0>;
508 compatible = "snps,designware-i2c";
509 reg = <0xffc04000 0x1000>;
510 clocks = <&l4_sp_clk>;
Dinh Nguyen449ff9c2018-04-04 17:18:23 -0500511 resets = <&rst I2C0_RESET>;
512 reset-names = "i2c";
Stefan Roese51c580c2014-11-07 14:10:41 +0100513 interrupts = <0 158 0x4>;
514 status = "disabled";
515 };
516
517 i2c1: i2c@ffc05000 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 compatible = "snps,designware-i2c";
521 reg = <0xffc05000 0x1000>;
522 clocks = <&l4_sp_clk>;
Dinh Nguyen449ff9c2018-04-04 17:18:23 -0500523 resets = <&rst I2C1_RESET>;
524 reset-names = "i2c";
Stefan Roese51c580c2014-11-07 14:10:41 +0100525 interrupts = <0 159 0x4>;
526 status = "disabled";
527 };
528
529 i2c2: i2c@ffc06000 {
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "snps,designware-i2c";
533 reg = <0xffc06000 0x1000>;
534 clocks = <&l4_sp_clk>;
Dinh Nguyen449ff9c2018-04-04 17:18:23 -0500535 resets = <&rst I2C2_RESET>;
536 reset-names = "i2c";
Stefan Roese51c580c2014-11-07 14:10:41 +0100537 interrupts = <0 160 0x4>;
538 status = "disabled";
539 };
540
541 i2c3: i2c@ffc07000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "snps,designware-i2c";
545 reg = <0xffc07000 0x1000>;
546 clocks = <&l4_sp_clk>;
Dinh Nguyen449ff9c2018-04-04 17:18:23 -0500547 resets = <&rst I2C3_RESET>;
548 reset-names = "i2c";
Stefan Roese51c580c2014-11-07 14:10:41 +0100549 interrupts = <0 161 0x4>;
550 status = "disabled";
551 };
552
553 gpio0: gpio@ff708000 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "snps,dw-apb-gpio";
557 reg = <0xff708000 0x1000>;
558 clocks = <&per_base_clk>;
559 status = "disabled";
560
561 porta: gpio-controller@0 {
562 compatible = "snps,dw-apb-gpio-port";
Marek Vasut660f53b2015-08-10 17:20:23 +0200563 bank-name = "porta";
Stefan Roese51c580c2014-11-07 14:10:41 +0100564 gpio-controller;
565 #gpio-cells = <2>;
566 snps,nr-gpios = <29>;
567 reg = <0>;
568 interrupt-controller;
569 #interrupt-cells = <2>;
570 interrupts = <0 164 4>;
571 };
572 };
573
574 gpio1: gpio@ff709000 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 compatible = "snps,dw-apb-gpio";
578 reg = <0xff709000 0x1000>;
579 clocks = <&per_base_clk>;
580 status = "disabled";
581
582 portb: gpio-controller@0 {
583 compatible = "snps,dw-apb-gpio-port";
Marek Vasut660f53b2015-08-10 17:20:23 +0200584 bank-name = "portb";
Stefan Roese51c580c2014-11-07 14:10:41 +0100585 gpio-controller;
586 #gpio-cells = <2>;
587 snps,nr-gpios = <29>;
588 reg = <0>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
591 interrupts = <0 165 4>;
592 };
593 };
594
595 gpio2: gpio@ff70a000 {
596 #address-cells = <1>;
597 #size-cells = <0>;
598 compatible = "snps,dw-apb-gpio";
599 reg = <0xff70a000 0x1000>;
600 clocks = <&per_base_clk>;
601 status = "disabled";
602
603 portc: gpio-controller@0 {
604 compatible = "snps,dw-apb-gpio-port";
Marek Vasut660f53b2015-08-10 17:20:23 +0200605 bank-name = "portc";
Stefan Roese51c580c2014-11-07 14:10:41 +0100606 gpio-controller;
607 #gpio-cells = <2>;
608 snps,nr-gpios = <27>;
609 reg = <0>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
612 interrupts = <0 166 4>;
613 };
614 };
615
616 sdr: sdr@ffc25000 {
617 compatible = "syscon";
618 reg = <0xffc25000 0x1000>;
619 };
620
621 sdramedac {
622 compatible = "altr,sdram-edac";
623 altr,sdr-syscon = <&sdr>;
624 interrupts = <0 39 4>;
625 };
626
627 L2: l2-cache@fffef000 {
628 compatible = "arm,pl310-cache";
629 reg = <0xfffef000 0x1000>;
630 interrupts = <0 38 0x04>;
631 cache-unified;
632 cache-level = <2>;
633 arm,tag-latency = <1 1 1>;
634 arm,data-latency = <2 1 1>;
635 };
636
Marek Vasutafe13992015-08-02 22:55:24 +0200637 mmc0: dwmmc0@ff704000 {
Stefan Roese51c580c2014-11-07 14:10:41 +0100638 compatible = "altr,socfpga-dw-mshc";
639 reg = <0xff704000 0x1000>;
640 interrupts = <0 139 4>;
641 fifo-depth = <0x400>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
645 clock-names = "biu", "ciu";
646 };
647
Stefan Roese881f6a42014-11-07 12:37:50 +0100648 qspi: spi@ff705000 {
Simon Goldschmidt2a3a9992018-11-02 11:54:51 +0100649 compatible = "cdns,qspi-nor";
Stefan Roese881f6a42014-11-07 12:37:50 +0100650 #address-cells = <1>;
651 #size-cells = <0>;
652 reg = <0xff705000 0x1000>,
653 <0xffa00000 0x1000>;
654 interrupts = <0 151 4>;
655 clocks = <&qspi_clk>;
656 ext-decoder = <0>; /* external decoder */
Marek Vasut653cda82014-12-31 20:14:56 +0100657 num-cs = <4>;
Jason Rush6e62b172018-01-23 17:13:10 -0600658 cdns,fifo-depth = <128>;
659 cdns,fifo-width = <4>;
660 cdns,trigger-address = <0x00000000>;
Stefan Roese881f6a42014-11-07 12:37:50 +0100661 bus-num = <2>;
662 status = "disabled";
663 };
664
Stefan Roeseae79e2d2014-11-07 13:50:32 +0100665 spi0: spi@fff00000 {
Marek Vasut74114862014-12-31 20:14:55 +0100666 compatible = "snps,dw-apb-ssi";
Stefan Roeseae79e2d2014-11-07 13:50:32 +0100667 #address-cells = <1>;
668 #size-cells = <0>;
669 reg = <0xfff00000 0x1000>;
670 interrupts = <0 154 4>;
Marek Vasut653cda82014-12-31 20:14:56 +0100671 num-cs = <4>;
Stefan Roeseae79e2d2014-11-07 13:50:32 +0100672 bus-num = <0>;
673 tx-dma-channel = <&pdma 16>;
674 rx-dma-channel = <&pdma 17>;
675 clocks = <&per_base_clk>;
676 status = "disabled";
677 };
678
679 spi1: spi@fff01000 {
Marek Vasut74114862014-12-31 20:14:55 +0100680 compatible = "snps,dw-apb-ssi";
Stefan Roeseae79e2d2014-11-07 13:50:32 +0100681 #address-cells = <1>;
682 #size-cells = <0>;
683 reg = <0xfff01000 0x1000>;
684 interrupts = <0 156 4>;
Marek Vasut653cda82014-12-31 20:14:56 +0100685 num-cs = <4>;
Stefan Roeseae79e2d2014-11-07 13:50:32 +0100686 bus-num = <1>;
687 tx-dma-channel = <&pdma 20>;
688 rx-dma-channel = <&pdma 21>;
689 clocks = <&per_base_clk>;
690 status = "disabled";
691 };
692
Stefan Roese51c580c2014-11-07 14:10:41 +0100693 /* Local timer */
694 timer@fffec600 {
695 compatible = "arm,cortex-a9-twd-timer";
696 reg = <0xfffec600 0x100>;
697 interrupts = <1 13 0xf04>;
698 clocks = <&mpu_periph_clk>;
699 };
700
701 timer0: timer0@ffc08000 {
702 compatible = "snps,dw-apb-timer";
703 interrupts = <0 167 4>;
704 reg = <0xffc08000 0x1000>;
705 clocks = <&l4_sp_clk>;
706 clock-names = "timer";
707 };
708
709 timer1: timer1@ffc09000 {
710 compatible = "snps,dw-apb-timer";
711 interrupts = <0 168 4>;
712 reg = <0xffc09000 0x1000>;
713 clocks = <&l4_sp_clk>;
714 clock-names = "timer";
715 };
716
717 timer2: timer2@ffd00000 {
718 compatible = "snps,dw-apb-timer";
719 interrupts = <0 169 4>;
720 reg = <0xffd00000 0x1000>;
721 clocks = <&osc1>;
722 clock-names = "timer";
723 };
724
725 timer3: timer3@ffd01000 {
726 compatible = "snps,dw-apb-timer";
727 interrupts = <0 170 4>;
728 reg = <0xffd01000 0x1000>;
729 clocks = <&osc1>;
730 clock-names = "timer";
731 };
732
733 uart0: serial0@ffc02000 {
734 compatible = "snps,dw-apb-uart";
735 reg = <0xffc02000 0x1000>;
736 interrupts = <0 162 4>;
737 reg-shift = <2>;
738 reg-io-width = <4>;
739 clocks = <&l4_sp_clk>;
Marek Vasut73172752018-05-11 22:26:35 +0200740 clock-frequency = <100000000>;
Stefan Roese51c580c2014-11-07 14:10:41 +0100741 };
742
743 uart1: serial1@ffc03000 {
744 compatible = "snps,dw-apb-uart";
745 reg = <0xffc03000 0x1000>;
746 interrupts = <0 163 4>;
747 reg-shift = <2>;
748 reg-io-width = <4>;
749 clocks = <&l4_sp_clk>;
Marek Vasut73172752018-05-11 22:26:35 +0200750 clock-frequency = <100000000>;
Stefan Roese51c580c2014-11-07 14:10:41 +0100751 };
752
753 rst: rstmgr@ffd05000 {
754 #reset-cells = <1>;
755 compatible = "altr,rst-mgr";
756 reg = <0xffd05000 0x1000>;
757 };
758
759 usbphy0: usbphy@0 {
760 #phy-cells = <0>;
761 compatible = "usb-nop-xceiv";
762 status = "okay";
763 };
764
765 usb0: usb@ffb00000 {
766 compatible = "snps,dwc2";
767 reg = <0xffb00000 0xffff>;
768 interrupts = <0 125 4>;
769 clocks = <&usb_mp_clk>;
770 clock-names = "otg";
771 phys = <&usbphy0>;
772 phy-names = "usb2-phy";
773 status = "disabled";
774 };
775
776 usb1: usb@ffb40000 {
777 compatible = "snps,dwc2";
778 reg = <0xffb40000 0xffff>;
779 interrupts = <0 128 4>;
780 clocks = <&usb_mp_clk>;
781 clock-names = "otg";
782 phys = <&usbphy0>;
783 phy-names = "usb2-phy";
784 status = "disabled";
785 };
786
787 watchdog0: watchdog@ffd02000 {
788 compatible = "snps,dw-wdt";
789 reg = <0xffd02000 0x1000>;
790 interrupts = <0 171 4>;
791 clocks = <&osc1>;
792 status = "disabled";
793 };
794
795 watchdog1: watchdog@ffd03000 {
796 compatible = "snps,dw-wdt";
797 reg = <0xffd03000 0x1000>;
798 interrupts = <0 172 4>;
799 clocks = <&osc1>;
800 status = "disabled";
801 };
802
803 sysmgr: sysmgr@ffd08000 {
804 compatible = "altr,sys-mgr", "syscon";
805 reg = <0xffd08000 0x4000>;
806 };
807 };
808};