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Tom Warren9112ef82011-11-05 09:48:11 +00001/*
Tom Warrenedffa632012-05-22 07:33:47 +00002 * Copyright (c) 2010-2012 NVIDIA Corporation
Tom Warren9112ef82011-11-05 09:48:11 +00003 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
27#include <malloc.h>
28#include <spi.h>
29#include <asm/io.h>
30#include <asm/gpio.h>
31#include <asm/arch/clk_rst.h>
32#include <asm/arch/clock.h>
33#include <asm/arch/pinmux.h>
Simon Glass4560c7d2011-11-05 04:46:50 +000034#include <asm/arch/uart-spi-switch.h>
Tom Warrenedffa632012-05-22 07:33:47 +000035#include <asm/arch/tegra_spi.h>
Tom Warren9112ef82011-11-05 09:48:11 +000036
Tom Warren078078c2012-05-15 14:32:40 -070037#if defined(CONFIG_SPI_CORRUPTS_UART)
38 #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
39#else
40 #define corrupt_delay()
41#endif
42
Tom Warren9112ef82011-11-05 09:48:11 +000043struct tegra_spi_slave {
44 struct spi_slave slave;
45 struct spi_tegra *regs;
46 unsigned int freq;
47 unsigned int mode;
48};
49
50static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
51{
52 return container_of(slave, struct tegra_spi_slave, slave);
53}
54
55int spi_cs_is_valid(unsigned int bus, unsigned int cs)
56{
Allen Martin00a27492012-08-31 08:30:00 +000057 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
Tom Warren9112ef82011-11-05 09:48:11 +000058 if (bus != 0 || cs != 0)
59 return 0;
60 else
61 return 1;
62}
63
64struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
65 unsigned int max_hz, unsigned int mode)
66{
67 struct tegra_spi_slave *spi;
68
69 if (!spi_cs_is_valid(bus, cs)) {
70 printf("SPI error: unsupported bus %d / chip select %d\n",
71 bus, cs);
72 return NULL;
73 }
74
Tom Warren29f3e3f2012-09-04 17:00:24 -070075 if (max_hz > TEGRA_SPI_MAX_FREQ) {
Tom Warren9112ef82011-11-05 09:48:11 +000076 printf("SPI error: unsupported frequency %d Hz. Max frequency"
Tom Warren29f3e3f2012-09-04 17:00:24 -070077 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
Tom Warren9112ef82011-11-05 09:48:11 +000078 return NULL;
79 }
80
81 spi = malloc(sizeof(struct tegra_spi_slave));
82 if (!spi) {
83 printf("SPI error: malloc of SPI structure failed\n");
84 return NULL;
85 }
86 spi->slave.bus = bus;
87 spi->slave.cs = cs;
88 spi->freq = max_hz;
Tom Warren29f3e3f2012-09-04 17:00:24 -070089 spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
Tom Warren9112ef82011-11-05 09:48:11 +000090 spi->mode = mode;
91
92 return &spi->slave;
93}
94
95void spi_free_slave(struct spi_slave *slave)
96{
97 struct tegra_spi_slave *spi = to_tegra_spi(slave);
98
99 free(spi);
100}
101
102void spi_init(void)
103{
104 /* do nothing */
105}
106
107int spi_claim_bus(struct spi_slave *slave)
108{
109 struct tegra_spi_slave *spi = to_tegra_spi(slave);
110 struct spi_tegra *regs = spi->regs;
111 u32 reg;
112
113 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
114 clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
115
116 /* Clear stale status here */
117 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
118 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
119 writel(reg, &regs->status);
120 debug("spi_init: STATUS = %08x\n", readl(&regs->status));
121
122 /*
123 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
124 */
125 reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
126 if (spi->mode & 2)
127 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
128 clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
129 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
130 debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
131
132 /*
Allen Martin00a27492012-08-31 08:30:00 +0000133 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
Tom Warren9112ef82011-11-05 09:48:11 +0000134 * issue.
135 */
136 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
137 pinmux_tristate_disable(PINGRP_LSPI);
Simon Glass4560c7d2011-11-05 04:46:50 +0000138
139#ifndef CONFIG_SPI_UART_SWITCH
140 /*
141 * NOTE:
142 * Only set PinMux bits 3:2 to SPI here on boards that don't have the
143 * SPI UART switch or subsequent UART data won't go out! See
144 * spi_uart_switch().
145 */
146 /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
147#endif
Tom Warren9112ef82011-11-05 09:48:11 +0000148 return 0;
149}
150
151void spi_release_bus(struct spi_slave *slave)
152{
153 /*
154 * We can't release UART_DISABLE and set pinmux to UART4 here since
155 * some code (e,g, spi_flash_probe) uses printf() while the SPI
156 * bus is held. That is arguably bad, but it has the advantage of
157 * already being in the source tree.
158 */
159}
160
161void spi_cs_activate(struct spi_slave *slave)
162{
163 struct tegra_spi_slave *spi = to_tegra_spi(slave);
164
Simon Glass4560c7d2011-11-05 04:46:50 +0000165 pinmux_select_spi();
166
Tom Warren9112ef82011-11-05 09:48:11 +0000167 /* CS is negated on Tegra, so drive a 1 to get a 0 */
168 setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
Tom Warren078078c2012-05-15 14:32:40 -0700169
170 corrupt_delay(); /* Let UART settle */
Tom Warren9112ef82011-11-05 09:48:11 +0000171}
172
173void spi_cs_deactivate(struct spi_slave *slave)
174{
175 struct tegra_spi_slave *spi = to_tegra_spi(slave);
176
Tom Warren078078c2012-05-15 14:32:40 -0700177 pinmux_select_uart();
178
Tom Warren9112ef82011-11-05 09:48:11 +0000179 /* CS is negated on Tegra, so drive a 0 to get a 1 */
180 clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
Tom Warren078078c2012-05-15 14:32:40 -0700181
182 corrupt_delay(); /* Let SPI settle */
Tom Warren9112ef82011-11-05 09:48:11 +0000183}
184
185int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
186 const void *data_out, void *data_in, unsigned long flags)
187{
188 struct tegra_spi_slave *spi = to_tegra_spi(slave);
189 struct spi_tegra *regs = spi->regs;
190 u32 reg, tmpdout, tmpdin = 0;
191 const u8 *dout = data_out;
192 u8 *din = data_in;
193 int num_bytes;
194 int ret;
195
196 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
197 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
198 if (bitlen % 8)
199 return -1;
200 num_bytes = bitlen / 8;
201
202 ret = 0;
203
204 reg = readl(&regs->status);
205 writel(reg, &regs->status); /* Clear all SPI events via R/W */
206 debug("spi_xfer entry: STATUS = %08x\n", reg);
207
208 reg = readl(&regs->command);
209 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
210 writel(reg, &regs->command);
211 debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
212
213 if (flags & SPI_XFER_BEGIN)
214 spi_cs_activate(slave);
215
216 /* handle data in 32-bit chunks */
217 while (num_bytes > 0) {
218 int bytes;
219 int is_read = 0;
220 int tm, i;
221
222 tmpdout = 0;
223 bytes = (num_bytes > 4) ? 4 : num_bytes;
224
225 if (dout != NULL) {
226 for (i = 0; i < bytes; ++i)
227 tmpdout = (tmpdout << 8) | dout[i];
228 }
229
230 num_bytes -= bytes;
231 if (dout)
232 dout += bytes;
233
234 clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
235 bytes * 8 - 1);
236 writel(tmpdout, &regs->tx_fifo);
237 setbits_le32(&regs->command, SPI_CMD_GO);
238
239 /*
240 * Wait for SPI transmit FIFO to empty, or to time out.
241 * The RX FIFO status will be read and cleared last
242 */
243 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
244 u32 status;
245
246 status = readl(&regs->status);
247
248 /* We can exit when we've had both RX and TX activity */
249 if (is_read && (status & SPI_STAT_TXF_EMPTY))
250 break;
251
252 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
253 SPI_STAT_RDY)
254 tm++;
255
256 else if (!(status & SPI_STAT_RXF_EMPTY)) {
257 tmpdin = readl(&regs->rx_fifo);
258 is_read = 1;
259
260 /* swap bytes read in */
261 if (din != NULL) {
262 for (i = bytes - 1; i >= 0; --i) {
263 din[i] = tmpdin & 0xff;
264 tmpdin >>= 8;
265 }
266 din += bytes;
267 }
268 }
269 }
270
271 if (tm >= SPI_TIMEOUT)
272 ret = tm;
273
274 /* clear ACK RDY, etc. bits */
275 writel(readl(&regs->status), &regs->status);
276 }
277
278 if (flags & SPI_XFER_END)
279 spi_cs_deactivate(slave);
280
281 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
282 tmpdin, readl(&regs->status));
283
284 if (ret) {
285 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
286 return -1;
287 }
288
289 return 0;
290}