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Stelian Pop8e429b32008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop8e429b32008-05-08 18:52:23 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop8e429b32008-05-08 18:52:23 +02007 */
8
9#include <common.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040010#include <linux/sizes.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020011#include <asm/arch/at91sam9263.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020012#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010013#include <asm/arch/at91_common.h>
Jens Scharsig1b34f002010-02-03 22:47:18 +010014#include <asm/arch/at91_matrix.h>
15#include <asm/arch/at91_pio.h>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020016#include <asm/arch/clk.h>
Xu, Hongcd46b0f2011-06-10 21:31:26 +000017#include <asm/io.h>
18#include <asm/arch/gpio.h>
Ben Warren3ae071e2008-08-12 22:11:53 -070019#include <asm/arch/hardware.h>
Stelian Pop56a24792008-05-08 14:52:31 +020020#include <lcd.h>
21#include <atmel_lcdc.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020022#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
23#include <net.h>
24#endif
Ben Warren3ae071e2008-08-12 22:11:53 -070025#include <netdev.h>
Andreas Henriksson81724e02014-01-27 19:18:59 +010026#include <atmel_mci.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020027
28DECLARE_GLOBAL_DATA_PTR;
29
30/* ------------------------------------------------------------------------- */
31/*
32 * Miscelaneous platform dependent initialisations
33 */
34
Stelian Pop8e429b32008-05-08 18:52:23 +020035#ifdef CONFIG_CMD_NAND
36static void at91sam9263ek_nand_hw_init(void)
37{
38 unsigned long csa;
Xu, Hongcd46b0f2011-06-10 21:31:26 +000039 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
40 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
Stelian Pop8e429b32008-05-08 18:52:23 +020041
42 /* Enable CS3 */
Jens Scharsig1b34f002010-02-03 22:47:18 +010043 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
44 writel(csa, &matrix->csa[0]);
45
46 /* Enable CS3 */
Stelian Pop8e429b32008-05-08 18:52:23 +020047
48 /* Configure SMC CS3 for NAND/SmartMedia */
Jens Scharsig1b34f002010-02-03 22:47:18 +010049 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
51 &smc->cs[3].setup);
Stelian Pop8e429b32008-05-08 18:52:23 +020052
Jens Scharsig1b34f002010-02-03 22:47:18 +010053 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
55 &smc->cs[3].pulse);
56
57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
58 &smc->cs[3].cycle);
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61#ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63#else /* CONFIG_SYS_NAND_DBW_8 */
64 AT91_SMC_MODE_DBW_8 |
65#endif
66 AT91_SMC_MODE_TDF_CYCLE(2),
67 &smc->cs[3].mode);
68
Wenyou Yang70341e22016-02-03 10:16:50 +080069 at91_periph_clk_enable(ATMEL_ID_PIOA);
70 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
Stelian Pop8e429b32008-05-08 18:52:23 +020071
72 /* Configure RDY/BSY */
Xu, Hongcd46b0f2011-06-10 21:31:26 +000073 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Stelian Pop8e429b32008-05-08 18:52:23 +020074
75 /* Enable NandFlash */
Xu, Hongcd46b0f2011-06-10 21:31:26 +000076 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop8e429b32008-05-08 18:52:23 +020077}
78#endif
79
Stelian Pop8e429b32008-05-08 18:52:23 +020080#ifdef CONFIG_MACB
81static void at91sam9263ek_macb_hw_init(void)
82{
Xu, Hongcd46b0f2011-06-10 21:31:26 +000083 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
Heiko Schocher4535a242013-11-18 08:07:23 +010084
Wenyou Yang70341e22016-02-03 10:16:50 +080085 at91_periph_clk_enable(ATMEL_ID_EMAC);
Stelian Pop8e429b32008-05-08 18:52:23 +020086
87 /*
88 * Disable pull-up on:
89 * RXDV (PC25) => PHY normal mode (not Test mode)
90 * ERX0 (PE25) => PHY ADDR0
91 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
92 *
93 * PHY has internal pull-down
94 */
Jens Scharsig1b34f002010-02-03 22:47:18 +010095 writel(1 << 25, &pio->pioc.pudr);
96 writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
97
Heiko Schocher4535a242013-11-18 08:07:23 +010098 at91_phy_reset();
Stelian Pop19bd6882008-05-22 00:15:40 +020099
Stelian Pop8e429b32008-05-08 18:52:23 +0200100 /* Re-enable pull-up */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100101 writel(1 << 25, &pio->pioc.puer);
102 writel((1 << 25) | (1 <<26), &pio->pioe.puer);
Stelian Pop8e429b32008-05-08 18:52:23 +0200103
Jean-Christophe PLAGNIOL-VILLARDe2c04762009-03-21 21:08:00 +0100104 at91_macb_hw_init();
Stelian Pop8e429b32008-05-08 18:52:23 +0200105}
106#endif
107
Stelian Pop56a24792008-05-08 14:52:31 +0200108#ifdef CONFIG_LCD
109vidinfo_t panel_info = {
Jeroen Hofsteec346e462014-06-10 00:16:23 +0200110 .vl_col = 240,
111 .vl_row = 320,
112 .vl_clk = 4965000,
113 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
114 ATMEL_LCDC_INVFRAME_INVERTED,
115 .vl_bpix = 3,
116 .vl_tft = 1,
117 .vl_hsync_len = 5,
118 .vl_left_margin = 1,
119 .vl_right_margin = 33,
120 .vl_vsync_len = 1,
121 .vl_upper_margin = 1,
122 .vl_lower_margin = 0,
123 .mmio = ATMEL_BASE_LCDC,
Stelian Pop56a24792008-05-08 14:52:31 +0200124};
125
126void lcd_enable(void)
127{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100128 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
Stelian Pop56a24792008-05-08 14:52:31 +0200129}
130
131void lcd_disable(void)
132{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100133 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
Stelian Pop56a24792008-05-08 14:52:31 +0200134}
135
136static void at91sam9263ek_lcd_hw_init(void)
137{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100138 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
139 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
140 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
141 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
142 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
143 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
144 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
145 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
146 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
147 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
148 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
149 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
150 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
151 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
152 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
153 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
154 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
155 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
156 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
157 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
158 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
159 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
Stelian Pop56a24792008-05-08 14:52:31 +0200160
Wenyou Yang70341e22016-02-03 10:16:50 +0800161 at91_periph_clk_enable(ATMEL_ID_LCDC);
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000162 gd->fb_base = ATMEL_BASE_SRAM0;
Stelian Pop56a24792008-05-08 14:52:31 +0200163}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200164
165#ifdef CONFIG_LCD_INFO
166#include <nand.h>
167#include <version.h>
168
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900169#ifdef CONFIG_MTD_NOR_FLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200170extern flash_info_t flash_info[];
171#endif
172
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200173void lcd_show_board_info(void)
174{
175 ulong dram_size, nand_size;
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900176#ifdef CONFIG_MTD_NOR_FLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200177 ulong flash_size;
178#endif
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200179 int i;
180 char temp[32];
181
182 lcd_printf ("%s\n", U_BOOT_VERSION);
183 lcd_printf ("(C) 2008 ATMEL Corp\n");
184 lcd_printf ("at91support@atmel.com\n");
185 lcd_printf ("%s CPU at %s MHz\n",
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000186 ATMEL_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +0200187 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200188
189 dram_size = 0;
190 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
191 dram_size += gd->bd->bi_dram[i].size;
192 nand_size = 0;
193 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
Scott Woodb616d9b2016-05-30 13:57:55 -0500194 nand_size += nand_info[i]->size;
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900195#ifdef CONFIG_MTD_NOR_FLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200196 flash_size = 0;
197 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
198 flash_size += flash_info[i].size;
199#endif
200 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200201 dram_size >> 20,
202 nand_size >> 20 );
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900203#ifdef CONFIG_MTD_NOR_FLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200204 lcd_printf (",\n %ld MB NOR",
205 flash_size >> 20);
206#endif
207 lcd_puts ("\n");
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200208}
209#endif /* CONFIG_LCD_INFO */
Stelian Pop56a24792008-05-08 14:52:31 +0200210#endif
211
Andreas Henriksson81724e02014-01-27 19:18:59 +0100212#ifdef CONFIG_GENERIC_ATMEL_MCI
213int board_mmc_init(bd_t *bd)
214{
215 at91_mci_hw_init();
216
217 return atmel_mci_init((void *)ATMEL_BASE_MCI1);
218}
219#endif
220
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000221int board_early_init_f(void)
222{
Wenyou Yang70341e22016-02-03 10:16:50 +0800223 at91_periph_clk_enable(ATMEL_ID_PIOA);
224 at91_periph_clk_enable(ATMEL_ID_PIOB);
225 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000226
esw@bus-elektronik.de2feb7362012-03-19 04:25:59 +0000227 at91_seriald_hw_init();
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000228 return 0;
229}
230
Stelian Pop8e429b32008-05-08 18:52:23 +0200231int board_init(void)
232{
Stelian Pop8e429b32008-05-08 18:52:23 +0200233 /* arch number of AT91SAM9263EK-Board */
234 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
235 /* adress of boot parameters */
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000236 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Stelian Pop8e429b32008-05-08 18:52:23 +0200237
Stelian Pop8e429b32008-05-08 18:52:23 +0200238#ifdef CONFIG_CMD_NAND
239 at91sam9263ek_nand_hw_init();
240#endif
241#ifdef CONFIG_HAS_DATAFLASH
Jens Scharsig1b34f002010-02-03 22:47:18 +0100242 at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100243 at91_spi0_hw_init(1 << 0);
Stelian Pop8e429b32008-05-08 18:52:23 +0200244#endif
245#ifdef CONFIG_MACB
246 at91sam9263ek_macb_hw_init();
247#endif
248#ifdef CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARDf3f91f82009-03-21 21:08:00 +0100249 at91_uhp_hw_init();
Stelian Pop8e429b32008-05-08 18:52:23 +0200250#endif
Stelian Pop56a24792008-05-08 14:52:31 +0200251#ifdef CONFIG_LCD
252 at91sam9263ek_lcd_hw_init();
253#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200254 return 0;
255}
256
257int dram_init(void)
258{
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000259 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
260 CONFIG_SYS_SDRAM_SIZE);
261
Stelian Pop8e429b32008-05-08 18:52:23 +0200262 return 0;
263}
264
265#ifdef CONFIG_RESET_PHY_R
266void reset_phy(void)
267{
Stelian Pop8e429b32008-05-08 18:52:23 +0200268}
269#endif
Ben Warren3ae071e2008-08-12 22:11:53 -0700270
271int board_eth_init(bd_t *bis)
272{
273 int rc = 0;
274#ifdef CONFIG_MACB
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000275 rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
Ben Warren3ae071e2008-08-12 22:11:53 -0700276#endif
277 return rc;
278}