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Dan Malek35171dc2007-01-05 09:15:34 +01001/*
2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Dan Malek35171dc2007-01-05 09:15:34 +010011 */
12
13/* mpc8560ads board configuration file */
14/* please refer to doc/README.mpc85xx for more info */
15/* make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050016 * search for CONFIG_SERVERIP, etc. in this file
Dan Malek35171dc2007-01-05 09:15:34 +010017 */
18
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/* High Level Configuration Options */
23#define CONFIG_BOOKE 1 /* BOOKE */
24#define CONFIG_E500 1 /* BOOKE e500 family */
Dan Malek35171dc2007-01-05 09:15:34 +010025#define CONFIG_CPM2 1 /* has CPM2 */
26#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
Kumar Galaf0600542008-06-11 00:44:10 -050027#define CONFIG_MPC8560 1
Dan Malek35171dc2007-01-05 09:15:34 +010028
Wolfgang Denk28415b62011-07-25 15:15:44 +020029#define CONFIG_SYS_TEXT_BASE 0xFFF80000
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030
Wolfgang Denkf1152f82007-07-06 02:50:19 +020031#define CONFIG_PCI /* PCI ethernet support */
Gabor Juhos842033e2013-05-30 07:06:12 +000032#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020033#define CONFIG_TSEC_ENET /* tsec ethernet support*/
34#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
Dan Malek35171dc2007-01-05 09:15:34 +010035#define CONFIG_ENV_OVERWRITE
Dan Malek35171dc2007-01-05 09:15:34 +010036
Kumar Gala572b13a2008-01-16 09:11:53 -060037#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Dan Malek35171dc2007-01-05 09:15:34 +010038
39/* sysclk for MPC85xx
40 */
41
Wolfgang Denkf1152f82007-07-06 02:50:19 +020042#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
Dan Malek35171dc2007-01-05 09:15:34 +010043
44/* Blinkin' LEDs for Robert :-)
45*/
46#define CONFIG_SHOW_ACTIVITY 1
47
48/*
49 * These can be toggled for performance analysis, otherwise use default.
50 */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020051#define CONFIG_L2_CACHE /* toggle L2 cache */
52#define CONFIG_BTB /* toggle branch predition */
Dan Malek35171dc2007-01-05 09:15:34 +010053
Wolfgang Denk53677ef2008-05-20 16:00:29 +020054#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Dan Malek35171dc2007-01-05 09:15:34 +010055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
57#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
58#define CONFIG_SYS_MEMTEST_END 0x00400000
Dan Malek35171dc2007-01-05 09:15:34 +010059
60
Wolfgang Denkf1152f82007-07-06 02:50:19 +020061/* Localbus connector. There are many options that can be
Dan Malek35171dc2007-01-05 09:15:34 +010062 * connected here, including sdram or lots of flash.
63 * This address, however, is used to configure a 256M local bus
64 * window that includes the Config latch below.
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
67#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
Dan Malek35171dc2007-01-05 09:15:34 +010068
69/* There are various flash options used, we configure for the largest,
70 * which is 64Mbytes. The CFI works fine and will discover the proper
71 * sizes.
72 */
Wolfgang Denkee152982007-05-31 17:20:09 +020073#ifdef CONFIG_STXSSA_4M
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020075#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020077#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
79#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
Dan Malek35171dc2007-01-05 09:15:34 +010080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020082#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
84#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
85#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
Dan Malek35171dc2007-01-05 09:15:34 +010086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Dan Malek35171dc2007-01-05 09:15:34 +010088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_FLASH_PROTECTION
Dan Malek35171dc2007-01-05 09:15:34 +010090
91/* The configuration latch is Chip Select 1.
92 * It's an 8-bit latch in the lower 8 bits of the word.
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
95#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
96#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
Dan Malek35171dc2007-01-05 09:15:34 +010097
Wolfgang Denk14d0a022010-10-07 21:51:12 +020098#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dan Malek35171dc2007-01-05 09:15:34 +010099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
101#define CONFIG_SYS_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100102#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#undef CONFIG_SYS_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100104#endif
105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#ifdef CONFIG_SYS_RAMBOOT
107#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
Dan Malek35171dc2007-01-05 09:15:34 +0100108#endif
Timur Tabie46fedf2011-08-04 18:03:41 -0500109
110#define CONFIG_SYS_CCSRBAR 0xe0000000
111#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Dan Malek35171dc2007-01-05 09:15:34 +0100112
Kumar Gala0e7927d2008-08-27 01:04:07 -0500113/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700114#define CONFIG_SYS_FSL_DDR1
Kumar Gala0e7927d2008-08-27 01:04:07 -0500115#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
116#define CONFIG_DDR_SPD
117#undef CONFIG_FSL_DDR_INTERACTIVE
Dan Malek35171dc2007-01-05 09:15:34 +0100118
Kumar Gala0e7927d2008-08-27 01:04:07 -0500119#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Kumar Gala0e7927d2008-08-27 01:04:07 -0500120#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
Dan Malek35171dc2007-01-05 09:15:34 +0100121
Kumar Gala0e7927d2008-08-27 01:04:07 -0500122#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
125#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Dan Malek35171dc2007-01-05 09:15:34 +0100126
Kumar Gala0e7927d2008-08-27 01:04:07 -0500127#define CONFIG_NUM_DDR_CONTROLLERS 1
128#define CONFIG_DIMM_SLOTS_PER_CTLR 1
129#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
130
131/* I2C addresses of SPD EEPROMs */
132#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
Dan Malek35171dc2007-01-05 09:15:34 +0100133
134#undef CONFIG_CLOCKS_IN_MHZ
135
136/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
138#define CONFIG_SYS_OR2_PRELIM 0xfc006901
139#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
140#define CONFIG_SYS_LBC_LBCR 0x00000000
141#define CONFIG_SYS_LBC_LSRT 0x20000000
142#define CONFIG_SYS_LBC_MRTPR 0x20000000
143#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
144#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
145#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
146#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
147#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
Dan Malek35171dc2007-01-05 09:15:34 +0100148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_RAM_LOCK 1
150#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200151#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Dan Malek35171dc2007-01-05 09:15:34 +0100152
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Dan Malek35171dc2007-01-05 09:15:34 +0100155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
157#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dan Malek35171dc2007-01-05 09:15:34 +0100158
159/* Serial Port */
160#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_NS16550
162#define CONFIG_SYS_NS16550_SERIAL
163#define CONFIG_SYS_NS16550_REG_SIZE 1
164#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dan Malek35171dc2007-01-05 09:15:34 +0100165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_BAUDRATE_TABLE \
Dan Malek35171dc2007-01-05 09:15:34 +0100167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
170#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Dan Malek35171dc2007-01-05 09:15:34 +0100171
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200172#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500173#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Dan Malek35171dc2007-01-05 09:15:34 +0100175
Wolfgang Denk28415b62011-07-25 15:15:44 +0200176/* pass open firmware flat tree */
177#define CONFIG_OF_LIBFDT 1
178#define CONFIG_OF_BOARD_SETUP 1
179#define CONFIG_OF_STDOUT_VIA_ALIAS 1
180
Wolfgang Denke1893812007-10-12 15:49:39 +0200181/*
182 * I2C
183 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200184#define CONFIG_SYS_I2C
185#define CONFIG_SYS_I2C_FSL
186#define CONFIG_SYS_FSL_I2C_SPEED 400000
187#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
188#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#undef CONFIG_SYS_I2C_NOPROBES
Dan Malek35171dc2007-01-05 09:15:34 +0100190
Wolfgang Denke1893812007-10-12 15:49:39 +0200191/* I2C RTC */
192#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Wolfgang Denke1893812007-10-12 15:49:39 +0200194
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200195/* I2C EEPROM. AT24C32, we keep our environment in here.
Dan Malek35171dc2007-01-05 09:15:34 +0100196*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
198#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
199#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
200#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Dan Malek35171dc2007-01-05 09:15:34 +0100201
202/*
203 * Standard 8555 PCI mapping.
204 * Addresses are mapped 1-1.
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
207#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
208#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
209#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
210#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
211#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Dan Malek35171dc2007-01-05 09:15:34 +0100212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
214#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
215#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
216#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
217#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
218#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Dan Malek35171dc2007-01-05 09:15:34 +0100219
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200220#if defined(CONFIG_PCI) /* PCI Ethernet card */
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200221#define CONFIG_MPC85XX_PCI2 1
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200222#define CONFIG_PCI_PNP /* do pci plug-and-play */
Dan Malek35171dc2007-01-05 09:15:34 +0100223
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200224#define CONFIG_EEPRO100
225#define CONFIG_TULIP
Dan Malek35171dc2007-01-05 09:15:34 +0100226
227#if !defined(CONFIG_PCI_PNP)
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200228 #define PCI_ENET0_IOADDR 0xe0000000
229 #define PCI_ENET0_MEMADDR 0xe0000000
230 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Dan Malek35171dc2007-01-05 09:15:34 +0100231#endif
232
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200233#define CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Dan Malek35171dc2007-01-05 09:15:34 +0100235
236#endif /* CONFIG_PCI */
237
238#if defined(CONFIG_TSEC_ENET)
239
Dan Malek35171dc2007-01-05 09:15:34 +0100240#define CONFIG_MII 1 /* MII PHY management */
241
Kim Phillips255a35772007-05-16 16:52:19 -0500242#define CONFIG_TSEC1 1
243#define CONFIG_TSEC1_NAME "TSEC0"
244#define CONFIG_TSEC2 1
245#define CONFIG_TSEC2_NAME "TSEC1"
Dan Malek35171dc2007-01-05 09:15:34 +0100246
247#define TSEC1_PHY_ADDR 2
248#define TSEC2_PHY_ADDR 4
249#define TSEC1_PHYIDX 0
250#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500251#define TSEC1_FLAGS TSEC_GIGABIT
252#define TSEC2_FLAGS TSEC_GIGABIT
Dan Malek35171dc2007-01-05 09:15:34 +0100253#define CONFIG_ETHPRIME "TSEC0"
254
255#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
256
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200257#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
258#undef CONFIG_ETHER_NONE /* define if ether on something else */
259#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
Dan Malek35171dc2007-01-05 09:15:34 +0100260
261#if (CONFIG_ETHER_INDEX == 2)
262 /*
263 * - Rx-CLK is CLK13
264 * - Tx-CLK is CLK14
265 * - Select bus for bd/buffers
266 * - Full duplex
267 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000268 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
269 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
Dan Malek35171dc2007-01-05 09:15:34 +0100271#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
Dan Malek35171dc2007-01-05 09:15:34 +0100273#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274 #define CONFIG_SYS_FCC_PSMR 0
Dan Malek35171dc2007-01-05 09:15:34 +0100275#endif
276 #define FETH2_RST 0x01
277#elif (CONFIG_ETHER_INDEX == 3)
278 /* need more definitions here for FE3 */
279 #define FETH3_RST 0x80
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200280#endif /* CONFIG_ETHER_INDEX */
Dan Malek35171dc2007-01-05 09:15:34 +0100281
282/* MDIO is done through the TSEC0 control.
283*/
284#define CONFIG_MII /* MII PHY management */
285#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
286
287#endif
288
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200289/* Environment - default config is in flash, see below */
290#if 0 /* in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200291# define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200292# define CONFIG_ENV_OFFSET 0
293# define CONFIG_ENV_SIZE 2048
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200294#else /* in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200295# define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denkee152982007-05-31 17:20:09 +0200296# ifdef CONFIG_STXSSA_4M
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200297# define CONFIG_ENV_SECT_SIZE 0x20000
Wolfgang Denkee152982007-05-31 17:20:09 +0200298# else /* default configuration - 64 MiB flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200299# define CONFIG_ENV_SECT_SIZE 0x40000
Wolfgang Denkee152982007-05-31 17:20:09 +0200300# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200302# define CONFIG_ENV_SIZE 0x4000
303# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
304# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Dan Malek35171dc2007-01-05 09:15:34 +0100305#endif
306
Dan Malek35171dc2007-01-05 09:15:34 +0100307#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dan Malek35171dc2007-01-05 09:15:34 +0100309
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200310#define CONFIG_TIMESTAMP /* Print image info with ts */
311
Jon Loeliger2835e512007-06-13 13:22:08 -0500312
313/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500314 * BOOTP options
315 */
316#define CONFIG_BOOTP_BOOTFILESIZE
317#define CONFIG_BOOTP_BOOTPATH
318#define CONFIG_BOOTP_GATEWAY
319#define CONFIG_BOOTP_HOSTNAME
320
321
322/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500323 * Command line configuration.
324 */
Wolfgang Denke1893812007-10-12 15:49:39 +0200325#define CONFIG_CMD_DATE
326#define CONFIG_CMD_DHCP
327#define CONFIG_CMD_EEPROM
Jon Loeliger2835e512007-06-13 13:22:08 -0500328#define CONFIG_CMD_I2C
Wolfgang Denke1893812007-10-12 15:49:39 +0200329#define CONFIG_CMD_PING
330#define CONFIG_CMD_SNTP
Becky Bruce199e2622010-06-17 11:37:25 -0500331#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500332
333#if defined(CONFIG_PCI)
334 #define CONFIG_CMD_PCI
Dan Malek35171dc2007-01-05 09:15:34 +0100335#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500336
337#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
338 #define CONFIG_CMD_MII
339#endif
340
Joe Hershbergeref0f2f52015-06-22 16:15:30 -0500341#if !defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger2835e512007-06-13 13:22:08 -0500342 #define CONFIG_CMD_ELF
343#endif
344
Dan Malek35171dc2007-01-05 09:15:34 +0100345
346#undef CONFIG_WATCHDOG /* watchdog disabled */
347
348/*
349 * Miscellaneous configurable options
350 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligeref0df522007-07-04 22:31:07 -0500352#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dan Malek35171dc2007-01-05 09:15:34 +0100354#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dan Malek35171dc2007-01-05 09:15:34 +0100356#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
358#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
359#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
360#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
Dan Malek35171dc2007-01-05 09:15:34 +0100361
362/*
363 * For booting Linux, the board info and command line data
364 * have to be in the first 8 MB of memory, since this is
365 * the maximum mapped by the Linux kernel during initialization.
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Dan Malek35171dc2007-01-05 09:15:34 +0100368
Jon Loeligeref0df522007-07-04 22:31:07 -0500369#if defined(CONFIG_CMD_KGDB)
Dan Malek35171dc2007-01-05 09:15:34 +0100370#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Dan Malek35171dc2007-01-05 09:15:34 +0100371#endif
372
Dan Malek35171dc2007-01-05 09:15:34 +0100373#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500374#define CONFIG_HAS_ETH0
Dan Malek35171dc2007-01-05 09:15:34 +0100375#define CONFIG_HAS_ETH1
Dan Malek35171dc2007-01-05 09:15:34 +0100376#define CONFIG_HAS_ETH2
Dan Malek35171dc2007-01-05 09:15:34 +0100377#endif
378
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200379/*
380 * Environment in EEPROM is compatible with different flash sector sizes,
381 * but only little space is available, so we use a very simple setup.
382 * With environment in flash, we use a more powerful default configuration.
383 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200384#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200385
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200386#define CONFIG_BAUDRATE 38400
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200387
388#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
389#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
390#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200391#define CONFIG_SERVERIP 192.168.85.1
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200392#define CONFIG_IPADDR 192.168.85.60
Dan Malek35171dc2007-01-05 09:15:34 +0100393#define CONFIG_GATEWAYIP 192.168.85.1
394#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200395#define CONFIG_HOSTNAME STX_SSA
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000396#define CONFIG_ROOTPATH "/gppproot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000397#define CONFIG_BOOTFILE "uImage"
Dan Malek35171dc2007-01-05 09:15:34 +0100398#define CONFIG_LOADADDR 0x1000000
399
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200400#else /* ENV IS IN FLASH -- use a full-blown envionment */
401
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200402#define CONFIG_BAUDRATE 115200
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200403
404#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
405
406#define CONFIG_PREBOOT "echo;" \
407 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
408 "echo"
409
410#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
411
412#define CONFIG_EXTRA_ENV_SETTINGS \
413 "hostname=gp3ssa\0" \
414 "bootfile=/tftpboot/gp3ssa/uImage\0" \
415 "loadaddr=400000\0" \
416 "netdev=eth0\0" \
417 "consdev=ttyS1\0" \
418 "nfsargs=setenv bootargs root=/dev/nfs rw " \
419 "nfsroot=$serverip:$rootpath\0" \
420 "ramargs=setenv bootargs root=/dev/ram rw\0" \
421 "addip=setenv bootargs $bootargs " \
422 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
423 ":$hostname:$netdev:off panic=1\0" \
424 "addcons=setenv bootargs $bootargs " \
425 "console=$consdev,$baudrate\0" \
426 "flash_nfs=run nfsargs addip addcons;" \
427 "bootm $kernel_addr\0" \
428 "flash_self=run ramargs addip addcons;" \
429 "bootm $kernel_addr $ramdisk_addr\0" \
430 "net_nfs=tftp $loadaddr $bootfile;" \
431 "run nfsargs addip addcons;bootm\0" \
432 "rootpath=/opt/eldk/ppc_85xx\0" \
433 "kernel_addr=FC000000\0" \
434 "ramdisk_addr=FC200000\0" \
435 ""
436#define CONFIG_BOOTCOMMAND "run flash_self"
437
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200438#endif /* CONFIG_ENV_IS_IN_EEPROM */
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200439
Dan Malek35171dc2007-01-05 09:15:34 +0100440#endif /* __CONFIG_H */