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Heiko Schocher2605e902007-02-16 07:57:42 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher2605e902007-02-16 07:57:42 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090016#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Heiko Schocher2605e902007-02-16 07:57:42 +010017#define CONFIG_JUPITER 1 /* ... on Jupiter board */
18
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019/*
20 * Valid values for CONFIG_SYS_TEXT_BASE are:
21 * 0xFFF00000 boot high (standard configuration)
22 * 0x00100000 boot from RAM (for testing only)
23 */
24#ifndef CONFIG_SYS_TEXT_BASE
25#define CONFIG_SYS_TEXT_BASE 0xFFF00000
26#endif
27
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Heiko Schocher2605e902007-02-16 07:57:42 +010029
30#define CONFIG_BOARD_EARLY_INIT_R 1
31#define CONFIG_BOARD_EARLY_INIT_F 1
32
Becky Bruce31d82672008-05-08 19:02:12 -050033#define CONFIG_HIGH_BATS 1 /* High BATs supported */
34
Heiko Schocher2605e902007-02-16 07:57:42 +010035/*
36 * Serial console configuration
37 */
38#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schocher2605e902007-02-16 07:57:42 +010041
42/*
43 * PCI Mapping:
44 * 0x40000000 - 0x4fffffff - PCI Memory
45 * 0x50000000 - 0x50ffffff - PCI IO Space
46 */
Wolfgang Denk769104c2007-03-08 21:49:27 +010047/*#define CONFIG_PCI */
Heiko Schocher2605e902007-02-16 07:57:42 +010048
49#if defined(CONFIG_PCI)
50#define CONFIG_PCI_PNP 1
51#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050052#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Heiko Schocher2605e902007-02-16 07:57:42 +010053
54#define CONFIG_PCI_MEM_BUS 0x40000000
55#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
56#define CONFIG_PCI_MEM_SIZE 0x10000000
57
58#define CONFIG_PCI_IO_BUS 0x50000000
59#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
60#define CONFIG_PCI_IO_SIZE 0x01000000
Heiko Schocher2605e902007-02-16 07:57:42 +010061#endif
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_XLB_PIPELINING 1
Heiko Schocher2605e902007-02-16 07:57:42 +010064
Heiko Schocher2605e902007-02-16 07:57:42 +010065#define CONFIG_MII 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Heiko Schocher2605e902007-02-16 07:57:42 +010067
68/* Partitions */
69#define CONFIG_MAC_PARTITION
70#define CONFIG_DOS_PARTITION
71#define CONFIG_ISO_PARTITION
72
73#define CONFIG_TIMESTAMP /* Print image info with timestamp */
74
Jon Loeligerbc234c12007-07-04 22:32:51 -050075/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050076 * BOOTP options
77 */
78#define CONFIG_BOOTP_BOOTFILESIZE
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_GATEWAY
81#define CONFIG_BOOTP_HOSTNAME
82
Jon Loeliger7f5c0152007-07-10 09:38:02 -050083/*
Jon Loeligerbc234c12007-07-04 22:32:51 -050084 * Command line configuration.
85 */
Jon Loeligerbc234c12007-07-04 22:32:51 -050086
Jon Loeliger7f5c0152007-07-10 09:38:02 -050087#if defined(CONFIG_PCI)
88#define CODFIG_CMD_PCI
89#endif
90
Heiko Schocher2605e902007-02-16 07:57:42 +010091/*
92 * Autobooting
93 */
Heiko Schocher2605e902007-02-16 07:57:42 +010094
95#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010096 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Heiko Schocher2605e902007-02-16 07:57:42 +010097 "echo"
98
99#undef CONFIG_BOOTARGS
100
101#define CONFIG_EXTRA_ENV_SETTINGS \
102 "netdev=eth0\0" \
103 "nfsargs=setenv bootargs root=/dev/nfs rw " \
104 "nfsroot=${serverip}:${rootpath}\0" \
105 "ramargs=setenv bootargs root=/dev/ram rw\0" \
106 "addip=setenv bootargs ${bootargs} " \
107 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
108 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100109 "flash_nfs=run nfsargs addip addcons;" \
Heiko Schocher2605e902007-02-16 07:57:42 +0100110 "bootm ${kernel_addr}\0" \
111 "flash_self=run ramargs addip;" \
112 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100113 "addcons=setenv bootargs ${bootargs} console=${contyp}," \
Heiko Schocher8502e302007-03-13 09:40:59 +0100114 "${baudrate}\0" \
115 "contyp=ttyS0\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100116 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
Heiko Schocher8502e302007-03-13 09:40:59 +0100117 "bootm\0" \
118 "rootpath=/opt/eldk/ppc_6xx\0" \
Heiko Schocher2605e902007-02-16 07:57:42 +0100119 "bootfile=/tftpboot/jupiter/uImage\0" \
120 ""
121
122#define CONFIG_BOOTCOMMAND "run flash_self"
123
124/*
125 * IPB Bus clocking configuration.
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
Heiko Schocher2605e902007-02-16 07:57:42 +0100128
129#if 0
130/* pass open firmware flat tree */
Heiko Schocher2605e902007-02-16 07:57:42 +0100131#define OF_CPU "PowerPC,5200@0"
132#define OF_SOC "soc5200@f0000000"
133#define OF_TBCLK (bd->bi_busfreq / 8)
134#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
135#endif
136
137#if 0
138/*
139 * I2C configuration
140 */
141#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Heiko Schocher2605e902007-02-16 07:57:42 +0100143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
145#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocher2605e902007-02-16 07:57:42 +0100146
147/*
148 * EEPROM configuration
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
151#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
152#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
153#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
Heiko Schocher2605e902007-02-16 07:57:42 +0100154#endif
155
156/*
157 * Flash configuration
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_BASE 0xFF000000
160#define CONFIG_SYS_FLASH_SIZE 0x01000000
Heiko Schocher2605e902007-02-16 07:57:42 +0100161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Heiko Schocher2605e902007-02-16 07:57:42 +0100163
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200164#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
Heiko Schocher2605e902007-02-16 07:57:42 +0100165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
167#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocher2605e902007-02-16 07:57:42 +0100168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
Heiko Schocher2605e902007-02-16 07:57:42 +0100170
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200171#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_CFI
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
175#define CONFIG_SYS_UPDATE_FLASH_SIZE 1
176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Heiko Schocher2605e902007-02-16 07:57:42 +0100177
178/*
179 * Environment settings
180 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200181#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200182#define CONFIG_ENV_SIZE 0x20000
183#define CONFIG_ENV_SECT_SIZE 0x20000
Heiko Schocher2605e902007-02-16 07:57:42 +0100184#define CONFIG_ENV_OVERWRITE 1
185
Heiko Schocher8502e302007-03-13 09:40:59 +0100186/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
188#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher8502e302007-03-13 09:40:59 +0100189
Heiko Schocher2605e902007-02-16 07:57:42 +0100190/*
191 * Memory map
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_MBAR 0xF0000000
194#define CONFIG_SYS_SDRAM_BASE 0x00000000
195#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Heiko Schocher2605e902007-02-16 07:57:42 +0100196
197/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200199#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Heiko Schocher2605e902007-02-16 07:57:42 +0100200
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200201#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher2605e902007-02-16 07:57:42 +0100203
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
206# define CONFIG_SYS_RAMBOOT 1
Heiko Schocher2605e902007-02-16 07:57:42 +0100207#endif
208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
210#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
211#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher2605e902007-02-16 07:57:42 +0100212
213/*
214 * Ethernet configuration
215 */
216#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800217#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schocher2605e902007-02-16 07:57:42 +0100218/*
Ben Warren86321fc2009-02-05 23:58:25 -0800219 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Heiko Schocher2605e902007-02-16 07:57:42 +0100220 */
Ben Warren86321fc2009-02-05 23:58:25 -0800221/* #define CONFIG_MPC5xxx_FEC_MII10 */
Heiko Schocher2605e902007-02-16 07:57:42 +0100222#define CONFIG_PHY_ADDR 0x00
223
224/*
225 * GPIO configuration
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
Heiko Schocher2605e902007-02-16 07:57:42 +0100228
229/*
230 * Miscellaneous configurable options
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_LONGHELP /* undef to save memory */
Heiko Schocher8502e302007-03-13 09:40:59 +0100233
234#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jon Loeligerbc234c12007-07-04 22:32:51 -0500235#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocher2605e902007-02-16 07:57:42 +0100237#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocher2605e902007-02-16 07:57:42 +0100239#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
241#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
242#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocher2605e902007-02-16 07:57:42 +0100243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
245#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
246#define CONFIG_SYS_ALT_MEMTEST 1
Heiko Schocher2605e902007-02-16 07:57:42 +0100247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
Heiko Schocher2605e902007-02-16 07:57:42 +0100249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerbc234c12007-07-04 22:32:51 -0500251#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerbc234c12007-07-04 22:32:51 -0500253#endif
254
Heiko Schocher2605e902007-02-16 07:57:42 +0100255/*
256 * Various low-level settings
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
259#define CONFIG_SYS_HID0_FINAL HID0_ICE
Heiko Schocher2605e902007-02-16 07:57:42 +0100260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
262#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
263#define CONFIG_SYS_BOOTCS_CFG 0x00047801
264#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
265#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Heiko Schocher2605e902007-02-16 07:57:42 +0100266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_CS_BURST 0x00000000
268#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Heiko Schocher2605e902007-02-16 07:57:42 +0100269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Heiko Schocher2605e902007-02-16 07:57:42 +0100271
272#endif /* __CONFIG_H */