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Thomas Abrahame39448e2016-04-23 22:18:13 +05301/*
2 * Configuration settings for the Espresso7420 board.
3 * Copyright (C) 2016 Samsung Electronics
4 * Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_EXYNOS7420_COMMON_H
10#define __CONFIG_EXYNOS7420_COMMON_H
11
12/* High Level Configuration Options */
13#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14#define CONFIG_EXYNOS7420 /* Exynos7 Family */
15#define CONFIG_S5P
16
17#include <asm/arch/cpu.h> /* get chip and board defs */
18#include <linux/sizes.h>
19
20#define CONFIG_ARCH_CPU_INIT
Thomas Abrahame39448e2016-04-23 22:18:13 +053021#define CONFIG_BOARD_EARLY_INIT_F
22
23/* Size of malloc() pool before and after relocation */
24#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
25
26/* Miscellaneous configurable options */
27#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
28#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
29#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
30
31/* Boot Argument Buffer Size */
32#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
33
34/* select serial console configuration */
35#define CONFIG_BAUDRATE 115200
36
37/* FLASH and environment organization */
38#define CONFIG_SYS_NO_FLASH
39
40/* Timer input clock frequency */
41#define COUNTER_FREQUENCY 24000000
42
43/* Device Tree */
44#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
45
46/* IRAM Layout */
47#define CONFIG_IRAM_BASE 0x02100000
48#define CONFIG_IRAM_SIZE 0x58000
49#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
50
51/* Number of CPUs available */
52#define CONFIG_CORE_COUNT 0x8
53
54/* select serial console configuration */
55#define CONFIG_BAUDRATE 115200
Thomas Abrahame39448e2016-04-23 22:18:13 +053056
57#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
58
59#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
60#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
61#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
62#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
63#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
64#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
65#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
66#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
67#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
68#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
69#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
70#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
71#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
72#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
73#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
74#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
75
76/* Configuration of ENV Blocks */
77#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
78
79#define BOOT_TARGET_DEVICES(func) \
80 func(MMC, mmc, 1) \
81 func(MMC, mmc, 0) \
82
83#ifndef MEM_LAYOUT_ENV_SETTINGS
84#define MEM_LAYOUT_ENV_SETTINGS \
85 "bootm_size=0x10000000\0" \
86 "kernel_addr_r=0x42000000\0" \
87 "fdt_addr_r=0x43000000\0" \
88 "ramdisk_addr_r=0x43300000\0" \
89 "scriptaddr=0x50000000\0" \
90 "pxefile_addr_r=0x51000000\0"
91#endif
92
93#ifndef EXYNOS_DEVICE_SETTINGS
94#define EXYNOS_DEVICE_SETTINGS \
95 "stdin=serial\0" \
96 "stdout=serial\0" \
97 "stderr=serial\0"
98#endif
99
100#ifndef EXYNOS_FDTFILE_SETTING
101#define EXYNOS_FDTFILE_SETTING
102#endif
103
104#define CONFIG_EXTRA_ENV_SETTINGS \
105 EXYNOS_DEVICE_SETTINGS \
106 EXYNOS_FDTFILE_SETTING \
107 MEM_LAYOUT_ENV_SETTINGS
108
109#endif /* __CONFIG_EXYNOS7420_COMMON_H */