blob: b91e63d930caa17a7d74f7c6691596f96be7366a [file] [log] [blame]
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
9 *
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
12 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/*
20 * High Level Configuration Options
21 */
22
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010024#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026/*
27 * Valid values for CONFIG_SYS_TEXT_BASE are:
28 * 0xFFF00000 boot high (standard configuration)
29 * 0xFE000000 boot low
30 * 0x00100000 boot from RAM (for testing only)
31 */
32#ifndef CONFIG_SYS_TEXT_BASE
33#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
34#endif
35
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010036#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
37
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010038#define CONFIG_SYS_CACHELINE_SIZE 32
39
40/*
41 * Serial console configuration
42 */
43#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
44#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
45#define CONFIG_SYS_BAUDRATE_TABLE \
46 { 9600, 19200, 38400, 57600, 115200, 230400 }
47
48/*
49 * PCI Mapping:
50 * 0x40000000 - 0x4fffffff - PCI Memory
51 * 0x50000000 - 0x50ffffff - PCI IO Space
52 */
53#define CONFIG_PCI 1
54#define CONFIG_PCI_PNP 1
55#define CONFIG_PCI_SCAN_SHOW 1
Anatolij Gustschin4fc823d2011-10-13 05:19:17 +000056#define CONFIG_PCI_BOOTDELAY 250
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010057
58#define CONFIG_PCI_MEM_BUS 0x40000000
59#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60#define CONFIG_PCI_MEM_SIZE 0x10000000
61
62#define CONFIG_PCI_IO_BUS 0x50000000
63#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
64#define CONFIG_PCI_IO_SIZE 0x01000000
65
66/*
67 * Partitions
68 */
69#define CONFIG_DOS_PARTITION
70#define CONFIG_BZIP2
71
72/*
Anatolij Gustschina59996e2011-05-29 21:16:20 +000073 * Video
74 */
Anatolij Gustschina59996e2011-05-29 21:16:20 +000075
76#ifdef CONFIG_VIDEO
77#define CONFIG_VIDEO_MB862xx
78#define CONFIG_VIDEO_MB862xx_ACCEL
79#define CONFIG_VIDEO_CORALP
Anatolij Gustschina59996e2011-05-29 21:16:20 +000080#define CONFIG_VIDEO_LOGO
Anatolij Gustschin348de312011-07-16 10:26:50 +000081#define CONFIG_VIDEO_BMP_LOGO
Anatolij Gustschina59996e2011-05-29 21:16:20 +000082#define CONFIG_SPLASH_SCREEN
83#define CONFIG_VIDEO_BMP_GZIP
84#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
85
86/* Coral-PA clock frequency, geo and other both 133MHz */
87#define CONFIG_SYS_MB862xx_CCF 0x00050000
88/* Video SDRAM parameters */
89#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
90#endif
91
92/*
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010093 * Command line configuration.
94 */
Anatolij Gustschina59996e2011-05-29 21:16:20 +000095#ifdef CONFIG_VIDEO
96#define CONFIG_CMD_BMP
97#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010098#define CONFIG_CMD_DATE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010099#define CONFIG_CMD_DIAG
100#define CONFIG_CMD_EEPROM
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100101#define CONFIG_CMD_IDE
102#define CONFIG_CMD_IRQ
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100103#define CONFIG_CMD_PCI
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100104#define CONFIG_CMD_REGINFO
105#define CONFIG_CMD_SAVES
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100106
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200107#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100108#define CONFIG_SYS_LOWBOOT 1
109#endif
110
111/*
112 * Autobooting
113 */
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100114
115#undef CONFIG_BOOTARGS
116
Detlev Zundelff276502009-08-05 18:37:45 +0200117#define CONFIG_EXTRA_ENV_SETTINGS \
118 "fw_image=digsyMPC.img\0" \
119 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
120 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
121 "do mtc led $x; done\0" \
122 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
123 "else run mtcb_fw; fi\0" \
124 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
125 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
126 "mtcb_update=mtc led user1 orange;" \
127 "while mtc key; do ; done; run mtcb_2;\0" \
128 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
129 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
130 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
131 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
132 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
133 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
134 "run mtcb_wait_flickr mtcb_ds_1;\0" \
135 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
136 "source 400000; else run mtcb_error; fi\0" \
137 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
138 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
139 "else run mtcb_error; fi\0" \
140 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
141 "run mtcb_checkfw\0" \
142 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
143 "else run mtcb_error; fi\0" \
144 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
145 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
146 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
147 "mtcb_uledflckr=mtc led user1 orange 11\0" \
148 "mtcb_error=mtc led user1 red\0" \
149 "mtcb_clear=erase ff000000 ff0fffff\0" \
150 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
151 "mtcb_success=mtc led user1 green\0" \
152 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
153 "then run mtcb_doide; else run mtcb_error; fi\0" \
154 "mtcb_doide=mtc led user2 green 1;" \
155 "run mtcb_wait_flickr mtcb_di_1;\0" \
156 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
157 "else run mtcb_error; fi\0" \
158 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
159 "ramdisk_num_sector=16\0" \
160 "flash_base=ff000000\0" \
161 "flashdisk_size=e00000\0" \
162 "env_sector=fff60000\0" \
163 "flashdisk_start=ff100000\0" \
164 "load_cmd=tftp 400000 digsyMPC.img\0" \
165 "clear_cmd=erase ff000000 ff0fffff\0" \
166 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
167 "update_cmd=run load_cmd; " \
168 "iminfo 400000; " \
169 "run clear_cmd flash_cmd; " \
170 "iminfo ff000000\0" \
171 "spi_driver=yes\0" \
172 "spi_watchdog=no\0" \
173 "ftps_start=yes\0" \
174 "ftps_user1=admin\0" \
175 "ftps_pass1=admin\0" \
176 "ftps_base1=/\0" \
177 "ftps_home1=/\0" \
178 "plc_sio_srv=no\0" \
179 "plc_sio_baud=57600\0" \
180 "plc_sio_parity=no\0" \
181 "plc_sio_stop=1\0" \
182 "plc_sio_com=2\0" \
183 "plc_eth_srv=yes\0" \
184 "plc_eth_port=1200\0" \
185 "plc_root=/ide/\0" \
186 "diag_level=0\0" \
187 "webvisu=no\0" \
188 "plc_can1_routing=no\0" \
189 "plc_can1_baudrate=250\0" \
190 "plc_can2_routing=no\0" \
191 "plc_can2_baudrate=250\0" \
192 "plc_can3_routing=no\0" \
193 "plc_can3_baudrate=250\0" \
194 "plc_can4_routing=no\0" \
195 "plc_can4_baudrate=250\0" \
196 "netdev=eth0\0" \
197 "console=ttyPSC0\0" \
198 "kernel_addr_r=400000\0" \
199 "fdt_addr_r=600000\0" \
200 "nfsargs=setenv bootargs root=/dev/nfs rw " \
201 "nfsroot=${serverip}:${rootpath}\0" \
202 "addip=setenv bootargs ${bootargs} " \
203 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
204 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100205 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
Detlev Zundelff276502009-08-05 18:37:45 +0200206 "rootpath=/opt/eldk/ppc_6xx\0" \
207 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
208 "tftp ${fdt_addr_r} ${fdt_file};" \
209 "run nfsargs addip addcons;" \
210 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
211 "load=tftp 200000 ${u-boot}\0" \
212 "update=protect off FFF00000 +${filesize};" \
213 "erase FFF00000 +${filesize};" \
214 "cp.b 200000 FFF00000 ${filesize};" \
215 "protect on FFF00000 +${filesize}\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100216 ""
217
Detlev Zundelff276502009-08-05 18:37:45 +0200218#define CONFIG_BOOTCOMMAND "run mtcb_start"
219
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100220/*
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200221 * SPI configuration
222 */
223#define CONFIG_HARD_SPI 1
224#define CONFIG_MPC52XX_SPI 1
225
226/*
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100227 * I2C configuration
228 */
229#define CONFIG_HARD_I2C 1
230#define CONFIG_SYS_I2C_MODULE 1
231#define CONFIG_SYS_I2C_SPEED 100000
232#define CONFIG_SYS_I2C_SLAVE 0x7F
233
234/*
235 * EEPROM configuration
236 */
237#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
238#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
239#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
240#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
241
242/*
243 * RTC configuration
244 */
Heiko Schocher466f0132011-01-13 08:25:00 +0100245#if defined(CONFIG_DIGSY_REV5)
246#define CONFIG_SYS_I2C_RTC_ADDR 0x56
247#define CONFIG_RTC_RV3029
Heiko Schochera01ebd92011-03-28 09:24:23 +0200248/* Enable 5k Ohm trickle charge resistor */
249#define CONFIG_SYS_RV3029_TCR 0x20
Heiko Schocher466f0132011-01-13 08:25:00 +0100250#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100251#define CONFIG_RTC_DS1337
252#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Werner Pfisterc569ad62009-09-21 14:49:56 +0200253#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
Heiko Schocher466f0132011-01-13 08:25:00 +0100254#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100255
256/*
257 * Flash configuration
258 */
259#define CONFIG_SYS_FLASH_CFI 1
260#define CONFIG_FLASH_CFI_DRIVER 1
261
Heiko Schocher466f0132011-01-13 08:25:00 +0100262#if defined(CONFIG_DIGSY_REV5)
263#define CONFIG_SYS_FLASH_BASE 0xFE000000
264#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
265#define CONFIG_SYS_MAX_FLASH_BANKS 2
Heiko Schocher927d2ce2011-01-21 07:23:35 +0100266#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
267 CONFIG_SYS_FLASH_BASE_CS1}
Heiko Schocher466f0132011-01-13 08:25:00 +0100268#define CONFIG_SYS_UPDATE_FLASH_SIZE
269#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
270#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100271#define CONFIG_SYS_FLASH_BASE 0xFF000000
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100272#define CONFIG_SYS_MAX_FLASH_BANKS 1
Heiko Schocher466f0132011-01-13 08:25:00 +0100273#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
274#endif
275
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100276#define CONFIG_SYS_MAX_FLASH_SECT 256
277#define CONFIG_FLASH_16BIT
278#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Heiko Schocher466f0132011-01-13 08:25:00 +0100279#define CONFIG_SYS_FLASH_SIZE 0x01000000
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100280#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
281#define CONFIG_SYS_FLASH_WRITE_TOUT 500
282
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100283#define OF_CPU "PowerPC,5200@0"
284#define OF_SOC "soc5200@f0000000"
285#define OF_TBCLK (bd->bi_busfreq / 4)
286
287#define CONFIG_BOARD_EARLY_INIT_R
288#define CONFIG_MISC_INIT_R
289
290/*
291 * Environment settings
292 */
293#define CONFIG_ENV_IS_IN_FLASH 1
294#if defined(CONFIG_LOWBOOT)
295#define CONFIG_ENV_ADDR 0xFF060000
296#else /* CONFIG_LOWBOOT */
297#define CONFIG_ENV_ADDR 0xFFF60000
298#endif /* CONFIG_LOWBOOT */
299#define CONFIG_ENV_SIZE 0x10000
300#define CONFIG_ENV_SECT_SIZE 0x20000
301#define CONFIG_ENV_OVERWRITE 1
302
303/*
304 * Memory map
305 */
306#define CONFIG_SYS_MBAR 0xF0000000
307#define CONFIG_SYS_SDRAM_BASE 0x00000000
308#if !defined(CONFIG_SYS_LOWBOOT)
309#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
310#else
311#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
312#endif
313
314/*
315 * Use SRAM until RAM will be available
316 */
317#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200318#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100319
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100320#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200321 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100322#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
323
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200324#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100325#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
326#define CONFIG_SYS_RAMBOOT 1
327#endif
328
329#define CONFIG_SYS_MONITOR_LEN (256 << 10)
330#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
331#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
332
333/*
334 * Ethernet configuration
335 */
336#define CONFIG_MPC5xxx_FEC 1
337#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schocher1b414932011-04-03 20:10:20 +0000338#if defined(CONFIG_DIGSY_REV5)
339#define CONFIG_PHY_ADDR 0x01
340#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100341#define CONFIG_PHY_ADDR 0x00
Heiko Schocher1b414932011-04-03 20:10:20 +0000342#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100343#define CONFIG_PHY_RESET_DELAY 1000
344
345#define CONFIG_NETCONSOLE /* include NetConsole support */
346
347/*
348 * GPIO configuration
Grzegorz Bernacki12602332009-06-12 11:33:55 +0200349 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
350 * Bit 0 (mask 0x80000000) : 0x1
351 * SPI on Tmr2/3/4/5 pins
352 * Bit 2:3 (mask 0x30000000) : 0x2
353 * ATA cs0/1 on csb_4/5
354 * Bit 6:7 (mask 0x03000000) : 0x2
355 * Ethernet 100Mbit with MD
356 * Bits 12:15 (mask 0x000f0000): 0x5
357 * USB - Two UARTs
358 * Bits 18:19 (mask 0x00003000) : 0x2
359 * PSC3 - USB2 on PSC3
360 * Bits 20:23 (mask 0x00000f00) : 0x1
361 * PSC2 - CAN1&2 on PSC2 pins
362 * Bits 25:27 (mask 0x00000070) : 0x1
363 * PSC1 - AC97 functionality
364 * Bits 29:31 (mask 0x00000007) : 0x2
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100365 */
366#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
367
368/*
369 * Miscellaneous configurable options
370 */
371#define CONFIG_SYS_LONGHELP
372#define CONFIG_AUTO_COMPLETE 1
Grzegorz Bernackia781de12009-06-17 16:20:14 +0200373#define CONFIG_CMDLINE_EDITING 1
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100374
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100375#define CONFIG_MX_CYCLIC 1
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100376
377#define CONFIG_SYS_CBSIZE 1024
378#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
379#define CONFIG_SYS_MAXARGS 32
380#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
381
382#define CONFIG_SYS_ALT_MEMTEST
383#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
384#define CONFIG_SYS_MEMTEST_START 0x00010000
385#define CONFIG_SYS_MEMTEST_END 0x019fffff
386
387#define CONFIG_SYS_LOAD_ADDR 0x00100000
388
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100389/*
390 * Various low-level settings
391 */
392#define CONFIG_SYS_SDRAM_CS1 1
393#define CONFIG_SYS_XLB_PIPELINING 1
394
395#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
396#define CONFIG_SYS_HID0_FINAL HID0_ICE
397
398#if defined(CONFIG_SYS_LOWBOOT)
399#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
400#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
401#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
402#endif
403
404#define CONFIG_SYS_CS4_START 0x60000000
405#define CONFIG_SYS_CS4_SIZE 0x1000
406#define CONFIG_SYS_CS4_CFG 0x0008FC00
407
408#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
409#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
410#define CONFIG_SYS_CS0_CFG 0x0002DD00
411
Heiko Schocher466f0132011-01-13 08:25:00 +0100412#if defined(CONFIG_DIGSY_REV5)
413#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
414#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
415#define CONFIG_SYS_CS1_CFG 0x0002DD00
416#endif
417
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100418#define CONFIG_SYS_CS_BURST 0x00000000
419#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
420
421#if !defined(CONFIG_SYS_LOWBOOT)
422#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
423#else
424#define CONFIG_SYS_RESET_ADDRESS 0xff000100
425#endif
426
427/*
428 * USB
429 */
430#define CONFIG_USB_OHCI_NEW
431#define CONFIG_SYS_OHCI_BE_CONTROLLER
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100432
433#define CONFIG_USB_CLOCK 0x00013333
434#define CONFIG_USB_CONFIG 0x00002000
435
436#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
437#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
438#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
439#define CONFIG_SYS_USB_OHCI_CPU_INIT
440
441/*
442 * IDE/ATA
443 */
444#define CONFIG_IDE_RESET
445#define CONFIG_IDE_PREINIT
446
447#define CONFIG_SYS_ATA_CS_ON_I2C2
448#define CONFIG_SYS_IDE_MAXBUS 1
449#define CONFIG_SYS_IDE_MAXDEVICE 1
450
451#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
452#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
453#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
454#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
455#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
456#define CONFIG_SYS_ATA_STRIDE 4
457
458#define CONFIG_ATAPI 1
459#define CONFIG_LBA48 1
460
461#endif /* __CONFIG_H */