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Macpaul Lin6cb144b2010-10-19 17:05:51 +08001/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin6cb144b2010-10-19 17:05:51 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Masahiro Yamada7e3f94e2015-07-15 20:59:28 +090012#include <asm/arch-ag101/ag101.h>
Macpaul Lin6cb144b2010-10-19 17:05:51 +080013
14/*
15 * CPU and Board Configuration Options
16 */
17#define CONFIG_ADP_AG101P
18
19#define CONFIG_USE_INTERRUPT
20
21#define CONFIG_SKIP_LOWLEVEL_INIT
22
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080023#define CONFIG_SYS_GENERIC_GLOBAL_DATA
24
ken kuoe3c58b02013-06-08 11:14:12 +080025/*
26 * Definitions related to passing arguments to kernel.
27 */
28#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
29#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
30#define CONFIG_INITRD_TAG /* send initrd params */
31
Macpaul Lin6cb144b2010-10-19 17:05:51 +080032#ifndef CONFIG_SKIP_LOWLEVEL_INIT
33#define CONFIG_MEM_REMAP
34#endif
35
36#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080037#define CONFIG_SYS_TEXT_BASE 0x00500000
38#else
39#ifdef CONFIG_MEM_REMAP
40#define CONFIG_SYS_TEXT_BASE 0x80000000
Macpaul Lin6cb144b2010-10-19 17:05:51 +080041#else
42#define CONFIG_SYS_TEXT_BASE 0x00000000
43#endif
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +080044#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +080045
46/*
47 * Timer
48 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +080049#define CONFIG_SYS_CLK_FREQ 39062500
50#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
51
52/*
53 * Use Externel CLOCK or PCLK
54 */
55#undef CONFIG_FTRTC010_EXTCLK
56
57#ifndef CONFIG_FTRTC010_EXTCLK
58#define CONFIG_FTRTC010_PCLK
59#endif
60
61#ifdef CONFIG_FTRTC010_EXTCLK
62#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
63#else
64#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
65#endif
66
67#define TIMER_LOAD_VAL 0xffffffff
68
69/*
70 * Real Time Clock
71 */
72#define CONFIG_RTC_FTRTC010
73
74/*
75 * Real Time Clock Divider
76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
77 */
78#define OSC_5MHZ (5*1000000)
79#define OSC_CLK (4*OSC_5MHZ)
80#define RTC_DIV_COUNT (0.5) /* Why?? */
81
82/*
83 * Serial console configuration
84 */
85
86/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
87#define CONFIG_BAUDRATE 38400
88#define CONFIG_CONS_INDEX 1
Macpaul Lin6cb144b2010-10-19 17:05:51 +080089#define CONFIG_SYS_NS16550_SERIAL
90#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
91#define CONFIG_SYS_NS16550_REG_SIZE -4
92#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
93
Macpaul Lin6cb144b2010-10-19 17:05:51 +080094/*
95 * Ethernet
96 */
97#define CONFIG_FTMAC100
98
Macpaul Lin6cb144b2010-10-19 17:05:51 +080099
100/*
101 * SD (MMC) controller
102 */
103#define CONFIG_MMC
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800104#define CONFIG_GENERIC_MMC
105#define CONFIG_DOS_PARTITION
106#define CONFIG_FTSDC010
107#define CONFIG_FTSDC010_NUMBER 1
ken kuo61ccf082013-06-08 11:14:11 +0800108#define CONFIG_FTSDC010_SDIO
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800109
110/*
111 * Command line configuration.
112 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800113#define CONFIG_CMD_DATE
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800114
115/*
116 * Miscellaneous configurable options
117 */
118#define CONFIG_SYS_LONGHELP /* undef to save memory */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
120
121/* Print Buffer Size */
122#define CONFIG_SYS_PBSIZE \
123 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
124
125/* max number of command args */
126#define CONFIG_SYS_MAXARGS 16
127
128/* Boot Argument Buffer Size */
129#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
130
131/*
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800132 * Size of malloc() pool
133 */
134/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
135#define CONFIG_SYS_MALLOC_LEN (512 << 10)
136
137/*
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800138 * AHB Controller configuration
139 */
140#define CONFIG_FTAHBC020S
141
142#ifdef CONFIG_FTAHBC020S
143#include <faraday/ftahbc020s.h>
144
145/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
146#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
147
148/*
149 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
150 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
151 * in C language.
152 */
153#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
154 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
155 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
156#endif
157
158/*
159 * Watchdog
160 */
161#define CONFIG_FTWDT010_WATCHDOG
162
163/*
164 * PMU Power controller configuration
165 */
166#define CONFIG_PMU
167#define CONFIG_FTPMU010_POWER
168
169#ifdef CONFIG_FTPMU010_POWER
170#include <faraday/ftpmu010.h>
171#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
172#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
173 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
174 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
175 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
176 FTPMU010_SDRAMHTC_CKE_DCSR | \
177 FTPMU010_SDRAMHTC_DQM_DCSR | \
178 FTPMU010_SDRAMHTC_SDCLK_DCSR)
179#endif
180
181/*
182 * SDRAM controller configuration
183 */
184#define CONFIG_FTSDMC021
185
186#ifdef CONFIG_FTSDMC021
187#include <faraday/ftsdmc021.h>
188
189#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
190 FTSDMC021_TP1_TRP(1) | \
191 FTSDMC021_TP1_TRCD(1) | \
192 FTSDMC021_TP1_TRF(3) | \
193 FTSDMC021_TP1_TWR(1) | \
194 FTSDMC021_TP1_TCL(2))
195
196#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
197 FTSDMC021_TP2_INI_REFT(8) | \
198 FTSDMC021_TP2_REF_INTV(0x180))
199
200/*
201 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
202 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
203 * C language.
204 */
205#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
206 FTSDMC021_CR1_DSZ(3) | \
207 FTSDMC021_CR1_MBW(2) | \
208 FTSDMC021_CR1_BNKSIZE(6))
209
210#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
211 FTSDMC021_CR2_IREF | \
212 FTSDMC021_CR2_ISMR)
213
214#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
215#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
216 CONFIG_SYS_FTSDMC021_BANK0_BASE)
217
ken kuo3c016702013-06-08 11:14:09 +0800218#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
219 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
220#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
221 CONFIG_SYS_FTSDMC021_BANK1_BASE)
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800222#endif
223
224/*
225 * Physical Memory Map
226 */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800227#ifdef CONFIG_SKIP_LOWLEVEL_INIT
228#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
229#else
230#ifdef CONFIG_MEM_REMAP
231#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
232#else
233#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800234#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800235#endif
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800236
ken kuo3c016702013-06-08 11:14:09 +0800237#define PHYS_SDRAM_1 \
238 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800239
ken kuo3c016702013-06-08 11:14:09 +0800240#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800241
242#ifdef CONFIG_SKIP_LOWLEVEL_INIT
243#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
244#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
245#else
246#ifdef CONFIG_MEM_REMAP
247#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
248#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
249#else
250#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
251#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
252#endif
253#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800254
255#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
256
257#ifdef CONFIG_MEM_REMAP
258#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
259 GENERATED_GBL_DATA_SIZE)
260#else
261#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
262 GENERATED_GBL_DATA_SIZE)
263#endif /* CONFIG_MEM_REMAP */
264
265/*
266 * Load address and memory test area should agree with
Bin Menga1875592016-02-05 19:30:11 -0800267 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800268 */
269#define CONFIG_SYS_LOAD_ADDR 0x300000
270
271/* memtest works on 63 MB in DRAM */
272#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
273#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
274
275/*
276 * Static memory controller configuration
277 */
278#define CONFIG_FTSMC020
279
280#ifdef CONFIG_FTSMC020
281#include <faraday/ftsmc020.h>
282
283#define CONFIG_SYS_FTSMC020_CONFIGS { \
284 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
285 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
286}
287
288#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
289#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
290 FTSMC020_BANK_SIZE_32M | \
291 FTSMC020_BANK_MBW_32)
292
293#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
294 FTSMC020_TPR_AST(1) | \
295 FTSMC020_TPR_CTW(1) | \
296 FTSMC020_TPR_ATI(1) | \
297 FTSMC020_TPR_AT2(1) | \
298 FTSMC020_TPR_WTC(1) | \
299 FTSMC020_TPR_AHT(1) | \
300 FTSMC020_TPR_TRNA(1))
301#endif
302
303/*
304 * FLASH on ADP_AG101P is connected to BANK0
305 * Just disalbe the other BANK to avoid detection error.
306 */
307#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
308 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
309 FTSMC020_BANK_SIZE_32M | \
310 FTSMC020_BANK_MBW_32)
311
312#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
313 FTSMC020_TPR_CTW(3) | \
314 FTSMC020_TPR_ATI(0xf) | \
315 FTSMC020_TPR_AT2(3) | \
316 FTSMC020_TPR_WTC(3) | \
317 FTSMC020_TPR_AHT(3) | \
318 FTSMC020_TPR_TRNA(0xf))
319
320#define FTSMC020_BANK1_CONFIG (0x00)
321#define FTSMC020_BANK1_TIMING (0x00)
322#endif /* CONFIG_FTSMC020 */
323
324/*
325 * FLASH and environment organization
326 */
327/* use CFI framework */
328#define CONFIG_SYS_FLASH_CFI
329#define CONFIG_FLASH_CFI_DRIVER
330
331#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
332#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800333#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800334
335/* support JEDEC */
336
337/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
338#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800339#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
340#else
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800341#ifdef CONFIG_MEM_REMAP
342#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
343#else
344#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800345#endif
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800346#endif /* CONFIG_MEM_REMAP */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800347
348#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
349#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
350#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
351
352#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
353#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
354
355/* max number of memory banks */
356/*
357 * There are 4 banks supported for this Controller,
358 * but we have only 1 bank connected to flash on board
359 */
360#define CONFIG_SYS_MAX_FLASH_BANKS 1
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800361#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800362
363/* max number of sectors on one chip */
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800364#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800365#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800366#define CONFIG_SYS_MAX_FLASH_SECT 512
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800367
368/* environments */
369#define CONFIG_ENV_IS_IN_FLASH
370#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
371#define CONFIG_ENV_SIZE 8192
372#define CONFIG_ENV_OVERWRITE
373
374#endif /* __CONFIG_H */