blob: 2613a0f0934cb4725939e74534837a5b33c0444c [file] [log] [blame]
Shengzhou Liuaba80042014-11-24 17:11:55 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 QDS board configuration file
9 */
10
11#ifndef __T1024QDS_H
12#define __T1024QDS_H
13
14/* High Level Configuration Options */
Shengzhou Liuaba80042014-11-24 17:11:55 +080015#define CONFIG_BOOKE
16#define CONFIG_E500 /* BOOKE e500 family */
17#define CONFIG_E500MC /* BOOKE e500mc family */
18#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
19#define CONFIG_MP /* support multiple processors */
Shengzhou Liuaba80042014-11-24 17:11:55 +080020#define CONFIG_ENABLE_36BIT_PHYS
21
22#ifdef CONFIG_PHYS_64BIT
23#define CONFIG_ADDR_MAP 1
24#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
25#endif
26
27#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
28#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
29#define CONFIG_FSL_IFC /* Enable IFC Support */
30
31#define CONFIG_FSL_LAW /* Use common FSL init code */
32#define CONFIG_ENV_OVERWRITE
33
34#define CONFIG_DEEP_SLEEP
tang yuantian2c537642014-12-18 09:55:07 +080035#if defined(CONFIG_DEEP_SLEEP)
tang yuantian2c537642014-12-18 09:55:07 +080036#define CONFIG_BOARD_EARLY_INIT_F
37#endif
Shengzhou Liuaba80042014-11-24 17:11:55 +080038
Aneesh Bansalef6c55a2016-01-22 16:37:22 +053039#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
40
Shengzhou Liuaba80042014-11-24 17:11:55 +080041#ifdef CONFIG_RAMBOOT_PBL
42#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
Shengzhou Liuaba80042014-11-24 17:11:55 +080043#define CONFIG_SPL_FLUSH_IMAGE
44#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Shengzhou Liuaba80042014-11-24 17:11:55 +080045#define CONFIG_FSL_LAW /* Use common FSL init code */
46#define CONFIG_SYS_TEXT_BASE 0x00201000
47#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
48#define CONFIG_SPL_PAD_TO 0x40000
49#define CONFIG_SPL_MAX_SIZE 0x28000
50#define RESET_VECTOR_OFFSET 0x27FFC
51#define BOOT_PAGE_OFFSET 0x27000
52#ifdef CONFIG_SPL_BUILD
53#define CONFIG_SPL_SKIP_RELOCATE
54#define CONFIG_SPL_COMMON_INIT_DDR
55#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
56#define CONFIG_SYS_NO_FLASH
57#endif
58
59#ifdef CONFIG_NAND
Shengzhou Liuaba80042014-11-24 17:11:55 +080060#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
61#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
62#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
63#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
64#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Zhao Qiangec90ac72016-09-08 12:55:32 +080065#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
Shengzhou Liuaba80042014-11-24 17:11:55 +080066#define CONFIG_SPL_NAND_BOOT
67#endif
68
69#ifdef CONFIG_SPIFLASH
70#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liuaba80042014-11-24 17:11:55 +080071#define CONFIG_SPL_SPI_FLASH_MINIMAL
72#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
73#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
74#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
75#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
76#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
77#ifndef CONFIG_SPL_BUILD
78#define CONFIG_SYS_MPC85XX_NO_RESETVEC
79#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080080#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
Shengzhou Liuaba80042014-11-24 17:11:55 +080081#define CONFIG_SPL_SPI_BOOT
82#endif
83
84#ifdef CONFIG_SDCARD
85#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liuaba80042014-11-24 17:11:55 +080086#define CONFIG_SPL_MMC_MINIMAL
87#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
88#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
89#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
90#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
91#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
92#ifndef CONFIG_SPL_BUILD
93#define CONFIG_SYS_MPC85XX_NO_RESETVEC
94#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080095#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
Shengzhou Liuaba80042014-11-24 17:11:55 +080096#define CONFIG_SPL_MMC_BOOT
97#endif
98
99#endif /* CONFIG_RAMBOOT_PBL */
100
101#ifndef CONFIG_SYS_TEXT_BASE
102#define CONFIG_SYS_TEXT_BASE 0xeff40000
103#endif
104
105#ifndef CONFIG_RESET_VECTOR_ADDRESS
106#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
107#endif
108
109#ifndef CONFIG_SYS_NO_FLASH
110#define CONFIG_FLASH_CFI_DRIVER
111#define CONFIG_SYS_FLASH_CFI
112#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
113#endif
114
115/* PCIe Boot - Master */
116#define CONFIG_SRIO_PCIE_BOOT_MASTER
117/*
118 * for slave u-boot IMAGE instored in master memory space,
119 * PHYS must be aligned based on the SIZE
120 */
121#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
122#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
123#ifdef CONFIG_PHYS_64BIT
124#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
125#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
126#else
127#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
128#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
129#endif
130/*
131 * for slave UCODE and ENV instored in master memory space,
132 * PHYS must be aligned based on the SIZE
133 */
134#ifdef CONFIG_PHYS_64BIT
135#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
136#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
137#else
138#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
139#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
140#endif
141#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
142/* slave core release by master*/
143#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
144#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
145
146/* PCIe Boot - Slave */
147#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
148#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
149#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
150 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
151/* Set 1M boot space for PCIe boot */
152#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
153#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
154 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
155#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
156#define CONFIG_SYS_NO_FLASH
157#endif
158
159#if defined(CONFIG_SPIFLASH)
160#define CONFIG_SYS_EXTRA_ENV_RELOC
161#define CONFIG_ENV_IS_IN_SPI_FLASH
162#define CONFIG_ENV_SPI_BUS 0
163#define CONFIG_ENV_SPI_CS 0
164#define CONFIG_ENV_SPI_MAX_HZ 10000000
165#define CONFIG_ENV_SPI_MODE 0
166#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
167#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
168#define CONFIG_ENV_SECT_SIZE 0x10000
169#elif defined(CONFIG_SDCARD)
170#define CONFIG_SYS_EXTRA_ENV_RELOC
171#define CONFIG_ENV_IS_IN_MMC
172#define CONFIG_SYS_MMC_ENV_DEV 0
173#define CONFIG_ENV_SIZE 0x2000
174#define CONFIG_ENV_OFFSET (512 * 0x800)
175#elif defined(CONFIG_NAND)
176#define CONFIG_SYS_EXTRA_ENV_RELOC
177#define CONFIG_ENV_IS_IN_NAND
178#define CONFIG_ENV_SIZE 0x2000
179#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
180#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
181#define CONFIG_ENV_IS_IN_REMOTE
182#define CONFIG_ENV_ADDR 0xffe20000
183#define CONFIG_ENV_SIZE 0x2000
184#elif defined(CONFIG_ENV_IS_NOWHERE)
185#define CONFIG_ENV_SIZE 0x2000
186#else
187#define CONFIG_ENV_IS_IN_FLASH
188#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE 0x2000
190#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
191#endif
192
Shengzhou Liuaba80042014-11-24 17:11:55 +0800193#ifndef __ASSEMBLY__
194unsigned long get_board_sys_clk(void);
195unsigned long get_board_ddr_clk(void);
196#endif
197
198#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
199#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
200
201/*
202 * These can be toggled for performance analysis, otherwise use default.
203 */
204#define CONFIG_SYS_CACHE_STASHING
205#define CONFIG_BACKSIDE_L2_CACHE
206#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
207#define CONFIG_BTB /* toggle branch predition */
208#define CONFIG_DDR_ECC
209#ifdef CONFIG_DDR_ECC
210#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
211#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
212#endif
213
214#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
215#define CONFIG_SYS_MEMTEST_END 0x00400000
216#define CONFIG_SYS_ALT_MEMTEST
217#define CONFIG_PANIC_HANG /* do not reset board on panic */
218
219/*
220 * Config the L3 Cache as L3 SRAM
221 */
222#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
223#define CONFIG_SYS_L3_SIZE (256 << 10)
224#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
225#ifdef CONFIG_RAMBOOT_PBL
226#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
227#endif
228#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
229#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
230#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
231#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
232
233#ifdef CONFIG_PHYS_64BIT
234#define CONFIG_SYS_DCSRBAR 0xf0000000
235#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
236#endif
237
238/* EEPROM */
239#define CONFIG_ID_EEPROM
240#define CONFIG_SYS_I2C_EEPROM_NXID
241#define CONFIG_SYS_EEPROM_BUS_NUM 0
242#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
243#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
244#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
245#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
246
247/*
248 * DDR Setup
249 */
250#define CONFIG_VERY_BIG_RAM
251#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
252#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
253#define CONFIG_DIMM_SLOTS_PER_CTLR 1
254#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
255#define CONFIG_DDR_SPD
256#ifndef CONFIG_SYS_FSL_DDR4
257#define CONFIG_SYS_FSL_DDR3
258#endif
259
260#define CONFIG_SYS_SPD_BUS_NUM 0
261#define SPD_EEPROM_ADDRESS 0x51
262
263#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
264
265/*
266 * IFC Definitions
267 */
268#define CONFIG_SYS_FLASH_BASE 0xe0000000
269#ifdef CONFIG_PHYS_64BIT
270#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
271#else
272#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
273#endif
274
275#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
276#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
277 + 0x8000000) | \
278 CSPR_PORT_SIZE_16 | \
279 CSPR_MSEL_NOR | \
280 CSPR_V)
281#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
282#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
283 CSPR_PORT_SIZE_16 | \
284 CSPR_MSEL_NOR | \
285 CSPR_V)
286#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
287/* NOR Flash Timing Params */
288#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
289#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
290 FTIM0_NOR_TEADC(0x5) | \
291 FTIM0_NOR_TEAHC(0x5))
292#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
293 FTIM1_NOR_TRAD_NOR(0x1A) |\
294 FTIM1_NOR_TSEQRAD_NOR(0x13))
295#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
296 FTIM2_NOR_TCH(0x4) | \
297 FTIM2_NOR_TWPH(0x0E) | \
298 FTIM2_NOR_TWP(0x1c))
299#define CONFIG_SYS_NOR_FTIM3 0x0
300
301#define CONFIG_SYS_FLASH_QUIET_TEST
302#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
303
304#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
305#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
306#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
307#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
308
309#define CONFIG_SYS_FLASH_EMPTY_INFO
310#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
311 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
312#define CONFIG_FSL_QIXIS /* use common QIXIS code */
313#define QIXIS_BASE 0xffdf0000
314#ifdef CONFIG_PHYS_64BIT
315#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
316#else
317#define QIXIS_BASE_PHYS QIXIS_BASE
318#endif
319#define QIXIS_LBMAP_SWITCH 0x06
320#define QIXIS_LBMAP_MASK 0x0f
321#define QIXIS_LBMAP_SHIFT 0
322#define QIXIS_LBMAP_DFLTBANK 0x00
323#define QIXIS_LBMAP_ALTBANK 0x04
324#define QIXIS_RST_CTL_RESET 0x31
325#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
326#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
327#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
328#define QIXIS_RST_FORCE_MEM 0x01
329
330#define CONFIG_SYS_CSPR3_EXT (0xf)
331#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
332 | CSPR_PORT_SIZE_8 \
333 | CSPR_MSEL_GPCM \
334 | CSPR_V)
335#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
336#define CONFIG_SYS_CSOR3 0x0
337/* QIXIS Timing parameters for IFC CS3 */
338#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
339 FTIM0_GPCM_TEADC(0x0e) | \
340 FTIM0_GPCM_TEAHC(0x0e))
341#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
342 FTIM1_GPCM_TRAD(0x3f))
343#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
344 FTIM2_GPCM_TCH(0x8) | \
345 FTIM2_GPCM_TWP(0x1f))
346#define CONFIG_SYS_CS3_FTIM3 0x0
347
348#define CONFIG_NAND_FSL_IFC
349#define CONFIG_SYS_NAND_BASE 0xff800000
350#ifdef CONFIG_PHYS_64BIT
351#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
352#else
353#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
354#endif
355#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
356#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
357 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
358 | CSPR_MSEL_NAND /* MSEL = NAND */ \
359 | CSPR_V)
360#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
361
362#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
363 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
364 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
365 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
366 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
367 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
368 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
369
370#define CONFIG_SYS_NAND_ONFI_DETECTION
371
372/* ONFI NAND Flash mode0 Timing Params */
373#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
374 FTIM0_NAND_TWP(0x18) | \
375 FTIM0_NAND_TWCHT(0x07) | \
376 FTIM0_NAND_TWH(0x0a))
377#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
378 FTIM1_NAND_TWBE(0x39) | \
379 FTIM1_NAND_TRR(0x0e) | \
380 FTIM1_NAND_TRP(0x18))
381#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
382 FTIM2_NAND_TREH(0x0a) | \
383 FTIM2_NAND_TWHRE(0x1e))
384#define CONFIG_SYS_NAND_FTIM3 0x0
385
386#define CONFIG_SYS_NAND_DDR_LAW 11
387#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
388#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800389#define CONFIG_CMD_NAND
390
391#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
392
393#if defined(CONFIG_NAND)
394#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
395#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
396#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
397#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
398#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
399#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
400#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
401#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
402#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
403#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
404#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
405#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
406#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
407#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
408#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
409#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
410#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
411#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
412#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
413#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
414#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
415#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
416#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
417#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
418#else
419#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
420#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
421#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
422#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
423#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
424#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
425#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
426#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
427#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
428#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
429#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
430#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
431#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
432#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
433#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
434#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
435#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
436#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
437#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
438#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
439#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
440#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
441#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
442#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
443#endif
444
445#ifdef CONFIG_SPL_BUILD
446#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
447#else
448#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
449#endif
450
451#if defined(CONFIG_RAMBOOT_PBL)
452#define CONFIG_SYS_RAMBOOT
453#endif
454
455#define CONFIG_BOARD_EARLY_INIT_R
456#define CONFIG_MISC_INIT_R
457
458#define CONFIG_HWCONFIG
459
460/* define to use L1 as initial stack */
461#define CONFIG_L1_INIT_RAM
462#define CONFIG_SYS_INIT_RAM_LOCK
463#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
464#ifdef CONFIG_PHYS_64BIT
465#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700466#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liuaba80042014-11-24 17:11:55 +0800467/* The assembler doesn't like typecast */
468#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
469 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
470 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
471#else
York Sunb3142e22015-08-17 13:31:51 -0700472#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800473#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
474#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
475#endif
476#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
477
478#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
479 GENERATED_GBL_DATA_SIZE)
480#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
481
482#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
483#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
484
485/* Serial Port */
486#define CONFIG_CONS_INDEX 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800487#define CONFIG_SYS_NS16550_SERIAL
488#define CONFIG_SYS_NS16550_REG_SIZE 1
489#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
490
491#define CONFIG_SYS_BAUDRATE_TABLE \
492 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
493
494#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
495#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
496#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
497#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Shengzhou Liuaba80042014-11-24 17:11:55 +0800498
Shengzhou Liuaba80042014-11-24 17:11:55 +0800499/* Video */
500#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */
501#define CONFIG_FSL_DIU_FB
502#ifdef CONFIG_FSL_DIU_FB
503#define CONFIG_FSL_DIU_CH7301
504#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
Shengzhou Liuaba80042014-11-24 17:11:55 +0800505#define CONFIG_CMD_BMP
Shengzhou Liuaba80042014-11-24 17:11:55 +0800506#define CONFIG_VIDEO_LOGO
507#define CONFIG_VIDEO_BMP_LOGO
508#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
509/*
510 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
511 * disable empty flash sector detection, which is I/O-intensive.
512 */
513#undef CONFIG_SYS_FLASH_EMPTY_INFO
514#endif
515#endif
516
Shengzhou Liuaba80042014-11-24 17:11:55 +0800517/* I2C */
518#define CONFIG_SYS_I2C
519#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
520#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
521#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
522#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
523#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
524#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
525#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
526
527#define I2C_MUX_PCA_ADDR 0x77
528#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800529#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
530#define I2C_RETIMER_ADDR 0x18
Shengzhou Liuaba80042014-11-24 17:11:55 +0800531
532/* I2C bus multiplexer */
533#define I2C_MUX_CH_DEFAULT 0x8
534#define I2C_MUX_CH_DIU 0xC
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800535#define I2C_MUX_CH5 0xD
536#define I2C_MUX_CH7 0xF
Shengzhou Liuaba80042014-11-24 17:11:55 +0800537
538/* LDI/DVI Encoder for display */
539#define CONFIG_SYS_I2C_LDI_ADDR 0x38
540#define CONFIG_SYS_I2C_DVI_ADDR 0x75
541
542/*
543 * RTC configuration
544 */
545#define RTC
546#define CONFIG_RTC_DS3231 1
547#define CONFIG_SYS_I2C_RTC_ADDR 0x68
548
549/*
550 * eSPI - Enhanced SPI
551 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800552#ifndef CONFIG_SPL_BUILD
Shengzhou Liuaba80042014-11-24 17:11:55 +0800553#endif
Shengzhou Liuaba80042014-11-24 17:11:55 +0800554#define CONFIG_SPI_FLASH_BAR
555#define CONFIG_SF_DEFAULT_SPEED 10000000
556#define CONFIG_SF_DEFAULT_MODE 0
557
558/*
559 * General PCIe
560 * Memory space is mapped 1-1, but I/O space must start from 0.
561 */
562#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400563#define CONFIG_PCIE1 /* PCIE controller 1 */
564#define CONFIG_PCIE2 /* PCIE controller 2 */
565#define CONFIG_PCIE3 /* PCIE controller 3 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800566#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
567#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
568#define CONFIG_PCI_INDIRECT_BRIDGE
569
570#ifdef CONFIG_PCI
571/* controller 1, direct to uli, tgtid 3, Base address 20000 */
572#ifdef CONFIG_PCIE1
573#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
574#ifdef CONFIG_PHYS_64BIT
575#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
576#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
577#else
578#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
579#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
580#endif
581#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
582#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
583#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
584#ifdef CONFIG_PHYS_64BIT
585#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
586#else
587#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
588#endif
589#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
590#endif
591
592/* controller 2, Slot 2, tgtid 2, Base address 201000 */
593#ifdef CONFIG_PCIE2
594#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
595#ifdef CONFIG_PHYS_64BIT
596#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
597#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
598#else
599#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
600#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
601#endif
602#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
603#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
604#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
605#ifdef CONFIG_PHYS_64BIT
606#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
607#else
608#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
609#endif
610#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
611#endif
612
613/* controller 3, Slot 1, tgtid 1, Base address 202000 */
614#ifdef CONFIG_PCIE3
615#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
616#ifdef CONFIG_PHYS_64BIT
617#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
618#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
619#else
620#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
621#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
622#endif
623#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
624#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
625#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
626#ifdef CONFIG_PHYS_64BIT
627#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
628#else
629#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
630#endif
631#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
632#endif
633
634#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800635#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
636#define CONFIG_DOS_PARTITION
637#endif /* CONFIG_PCI */
638
639/*
640 *SATA
641 */
642#define CONFIG_FSL_SATA_V2
643#ifdef CONFIG_FSL_SATA_V2
644#define CONFIG_LIBATA
645#define CONFIG_FSL_SATA
646#define CONFIG_SYS_SATA_MAX_DEVICE 1
647#define CONFIG_SATA1
648#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
649#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
650#define CONFIG_LBA48
651#define CONFIG_CMD_SATA
652#define CONFIG_DOS_PARTITION
Shengzhou Liuaba80042014-11-24 17:11:55 +0800653#endif
654
655/*
656 * USB
657 */
658#define CONFIG_HAS_FSL_DR_USB
659
660#ifdef CONFIG_HAS_FSL_DR_USB
661#define CONFIG_USB_EHCI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800662#define CONFIG_USB_EHCI_FSL
663#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liuaba80042014-11-24 17:11:55 +0800664#endif
665
666/*
667 * SDHC
668 */
669#define CONFIG_MMC
670#ifdef CONFIG_MMC
671#define CONFIG_FSL_ESDHC
672#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Shengzhou Liuaba80042014-11-24 17:11:55 +0800673#define CONFIG_GENERIC_MMC
Shengzhou Liuaba80042014-11-24 17:11:55 +0800674#define CONFIG_DOS_PARTITION
675#endif
676
677/* Qman/Bman */
678#ifndef CONFIG_NOBQFMAN
679#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500680#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800681#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
682#ifdef CONFIG_PHYS_64BIT
683#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
684#else
685#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
686#endif
687#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500688#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
689#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
690#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
691#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
692#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
693 CONFIG_SYS_BMAN_CENA_SIZE)
694#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
695#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500696#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800697#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
698#ifdef CONFIG_PHYS_64BIT
699#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
700#else
701#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
702#endif
703#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500704#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
705#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
706#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
707#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
708#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
709 CONFIG_SYS_QMAN_CENA_SIZE)
710#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
711#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuaba80042014-11-24 17:11:55 +0800712
713#define CONFIG_SYS_DPAA_FMAN
714
715#define CONFIG_QE
716#define CONFIG_U_QE
717/* Default address of microcode for the Linux FMan driver */
718#if defined(CONFIG_SPIFLASH)
719/*
720 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
721 * env, so we got 0x110000.
722 */
723#define CONFIG_SYS_QE_FW_IN_SPIFLASH
724#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
725#define CONFIG_SYS_QE_FW_ADDR 0x130000
726#elif defined(CONFIG_SDCARD)
727/*
728 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
729 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
730 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
731 */
732#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
733#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
734#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
735#elif defined(CONFIG_NAND)
736#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
737#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
738#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
739#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
740/*
741 * Slave has no ucode locally, it can fetch this from remote. When implementing
742 * in two corenet boards, slave's ucode could be stored in master's memory
743 * space, the address can be mapped from slave TLB->slave LAW->
744 * slave SRIO or PCIE outbound window->master inbound window->
745 * master LAW->the ucode address in master's memory space.
746 */
747#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
748#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
749#else
750#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
751#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
752#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
753#endif
754#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
755#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
756#endif /* CONFIG_NOBQFMAN */
757
758#ifdef CONFIG_SYS_DPAA_FMAN
759#define CONFIG_FMAN_ENET
760#define CONFIG_PHYLIB_10G
761#define CONFIG_PHY_VITESSE
762#define CONFIG_PHY_REALTEK
763#define CONFIG_PHY_TERANETICS
764#define RGMII_PHY1_ADDR 0x1
765#define RGMII_PHY2_ADDR 0x2
766#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
767#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
768#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
769#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
770#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
771#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
772#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
773#endif
774
775#ifdef CONFIG_FMAN_ENET
776#define CONFIG_MII /* MII PHY management */
777#define CONFIG_ETHPRIME "FM1@DTSEC4"
778#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
779#endif
780
781/*
782 * Dynamic MTD Partition support with mtdparts
783 */
784#ifndef CONFIG_SYS_NO_FLASH
785#define CONFIG_MTD_DEVICE
786#define CONFIG_MTD_PARTITIONS
787#define CONFIG_CMD_MTDPARTS
788#define CONFIG_FLASH_CFI_MTD
789#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
790 "spi0=spife110000.0"
791#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
792 "128k(dtb),96m(fs),-(user);"\
793 "fff800000.flash:2m(uboot),9m(kernel),"\
794 "128k(dtb),96m(fs),-(user);spife110000.0:" \
795 "2m(uboot),9m(kernel),128k(dtb),-(user)"
796#endif
797
798/*
799 * Environment
800 */
801#define CONFIG_LOADS_ECHO /* echo on for serial download */
802#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
803
804/*
805 * Command line configuration.
806 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800807#define CONFIG_CMD_DATE
Shengzhou Liuaba80042014-11-24 17:11:55 +0800808#define CONFIG_CMD_EEPROM
Shengzhou Liuaba80042014-11-24 17:11:55 +0800809#define CONFIG_CMD_ERRATA
Shengzhou Liuaba80042014-11-24 17:11:55 +0800810#define CONFIG_CMD_IRQ
Shengzhou Liuaba80042014-11-24 17:11:55 +0800811#define CONFIG_CMD_REGINFO
Shengzhou Liuaba80042014-11-24 17:11:55 +0800812
813#ifdef CONFIG_PCI
814#define CONFIG_CMD_PCI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800815#endif
816
817/*
818 * Miscellaneous configurable options
819 */
820#define CONFIG_SYS_LONGHELP /* undef to save memory */
821#define CONFIG_CMDLINE_EDITING /* Command-line editing */
822#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
823#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800824#ifdef CONFIG_CMD_KGDB
825#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
826#else
827#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
828#endif
829#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
830#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
831#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
832
833/*
834 * For booting Linux, the board info and command line data
835 * have to be in the first 64 MB of memory, since this is
836 * the maximum mapped by the Linux kernel during initialization.
837 */
838#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
839#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
840
841#ifdef CONFIG_CMD_KGDB
842#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
843#endif
844
845/*
846 * Environment Configuration
847 */
848#define CONFIG_ROOTPATH "/opt/nfsroot"
849#define CONFIG_BOOTFILE "uImage"
850#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
851#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800852#define CONFIG_BAUDRATE 115200
853#define __USB_PHY_TYPE utmi
854
Shengzhou Liuaba80042014-11-24 17:11:55 +0800855#define CONFIG_EXTRA_ENV_SETTINGS \
856 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
857 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
858 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
859 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
860 "fdtfile=t1024qds/t1024qds.dtb\0" \
861 "netdev=eth0\0" \
862 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
863 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
864 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
865 "tftpflash=tftpboot $loadaddr $uboot && " \
866 "protect off $ubootaddr +$filesize && " \
867 "erase $ubootaddr +$filesize && " \
868 "cp.b $loadaddr $ubootaddr $filesize && " \
869 "protect on $ubootaddr +$filesize && " \
870 "cmp.b $loadaddr $ubootaddr $filesize\0" \
871 "consoledev=ttyS0\0" \
872 "ramdiskaddr=2000000\0" \
873 "fdtaddr=d00000\0" \
874 "bdev=sda3\0"
875
876#define CONFIG_LINUX \
877 "setenv bootargs root=/dev/ram rw " \
878 "console=$consoledev,$baudrate $othbootargs;" \
879 "setenv ramdiskaddr 0x02000000;" \
880 "setenv fdtaddr 0x00c00000;" \
881 "setenv loadaddr 0x1000000;" \
882 "bootm $loadaddr $ramdiskaddr $fdtaddr"
883
884#define CONFIG_NFSBOOTCOMMAND \
885 "setenv bootargs root=/dev/nfs rw " \
886 "nfsroot=$serverip:$rootpath " \
887 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
888 "console=$consoledev,$baudrate $othbootargs;" \
889 "tftp $loadaddr $bootfile;" \
890 "tftp $fdtaddr $fdtfile;" \
891 "bootm $loadaddr - $fdtaddr"
892
893#define CONFIG_BOOTCOMMAND CONFIG_LINUX
894
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530895/* Hash command with SHA acceleration supported in hardware */
896#ifdef CONFIG_FSL_CAAM
897#define CONFIG_CMD_HASH
898#define CONFIG_SHA_HW_ACCEL
899#endif
900
Shengzhou Liuaba80042014-11-24 17:11:55 +0800901#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530902
Shengzhou Liuaba80042014-11-24 17:11:55 +0800903#endif /* __T1024QDS_H */