blob: de2b4d8c49af2840ebca6007fa9573392b342a9f [file] [log] [blame]
Andy Fleming67431052007-04-23 02:54:25 -05001/*
Kumar Gala5f7bbd12011-01-04 18:01:49 -06002 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
Andy Fleming67431052007-04-23 02:54:25 -05003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming67431052007-04-23 02:54:25 -05005 */
6
7/*
8 * mpc8568mds board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* High Level Configuration Options */
14#define CONFIG_BOOKE 1 /* BOOKE */
Andy Flemingda9d4612007-08-14 00:14:25 -050015#define CONFIG_E500 1 /* BOOKE e500 family */
Andy Fleming67431052007-04-23 02:54:25 -050016#define CONFIG_MPC8568 1 /* MPC8568 specific */
17#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
18
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xfff80000
20
Kumar Gala5f7bbd12011-01-04 18:01:49 -060021#define CONFIG_SYS_SRIO
22#define CONFIG_SRIO1 /* SRIO port 1 */
23
Haiying Wang1563f562007-11-14 15:52:06 -050024#define CONFIG_PCI 1 /* Enable PCI/PCIE */
25#define CONFIG_PCI1 1 /* PCI controller */
26#define CONFIG_PCIE1 1 /* PCIE controller */
27#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000028#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ff3de62007-12-07 12:17:34 -060029#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050030#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020031#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingb96c83d2007-08-15 20:03:34 -050032#define CONFIG_QE /* Enable QE */
Andy Fleming67431052007-04-23 02:54:25 -050033#define CONFIG_ENV_OVERWRITE
Kumar Gala4d3521c2008-01-16 09:15:29 -060034#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Andy Fleming67431052007-04-23 02:54:25 -050035
Andy Fleming67431052007-04-23 02:54:25 -050036#ifndef __ASSEMBLY__
37extern unsigned long get_clock_freq(void);
38#endif /*Replace a call to get_clock_freq (after it is implemented)*/
39#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
40
41/*
42 * These can be toggled for performance analysis, otherwise use default.
43 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_L2_CACHE /* toggle L2 cache */
Haiying Wang7a1ac412007-08-23 15:20:54 -040045#define CONFIG_BTB /* toggle branch predition */
Andy Fleming67431052007-04-23 02:54:25 -050046
47/*
48 * Only possible on E500 Version 2 or newer cores.
49 */
50#define CONFIG_ENABLE_36BIT_PHYS 1
51
Andy Fleming67431052007-04-23 02:54:25 -050052#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
53
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
55#define CONFIG_SYS_MEMTEST_END 0x00400000
Andy Fleming67431052007-04-23 02:54:25 -050056
Timur Tabie46fedf2011-08-04 18:03:41 -050057#define CONFIG_SYS_CCSRBAR 0xe0000000
58#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Andy Fleming67431052007-04-23 02:54:25 -050059
Jon Loeligere6f5b352008-03-18 13:51:05 -050060/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070061#define CONFIG_SYS_FSL_DDR2
Jon Loeligere6f5b352008-03-18 13:51:05 -050062#undef CONFIG_FSL_DDR_INTERACTIVE
63#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
64#define CONFIG_DDR_SPD
Dave Liu9b0ad1b2008-10-28 17:53:38 +080065#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere6f5b352008-03-18 13:51:05 -050066
67#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
70#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Andy Fleming67431052007-04-23 02:54:25 -050071
Jon Loeligere6f5b352008-03-18 13:51:05 -050072#define CONFIG_NUM_DDR_CONTROLLERS 1
73#define CONFIG_DIMM_SLOTS_PER_CTLR 1
74#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Andy Fleming67431052007-04-23 02:54:25 -050075
Jon Loeligere6f5b352008-03-18 13:51:05 -050076/* I2C addresses of SPD EEPROMs */
77#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
78
79/* Make sure required options are set */
Andy Fleming67431052007-04-23 02:54:25 -050080#ifndef CONFIG_SPD_EEPROM
81#error ("CONFIG_SPD_EEPROM is required")
82#endif
83
84#undef CONFIG_CLOCKS_IN_MHZ
85
Andy Fleming67431052007-04-23 02:54:25 -050086/*
87 * Local Bus Definitions
88 */
89
90/*
91 * FLASH on the Local Bus
92 * Two banks, 8M each, using the CFI driver.
93 * Boot from BR0/OR0 bank at 0xff00_0000
94 * Alternate BR1/OR1 bank at 0xff80_0000
95 *
96 * BR0, BR1:
97 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
98 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
99 * Port Size = 16 bits = BRx[19:20] = 10
100 * Use GPCM = BRx[24:26] = 000
101 * Valid = BRx[31] = 1
102 *
103 * 0 4 8 12 16 20 24 28
104 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
105 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
106 *
107 * OR0, OR1:
108 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
109 * Reserved ORx[17:18] = 11, confusion here?
110 * CSNT = ORx[20] = 1
111 * ACS = half cycle delay = ORx[21:22] = 11
112 * SCY = 6 = ORx[24:27] = 0110
113 * TRLX = use relaxed timing = ORx[29] = 1
114 * EAD = use external address latch delay = OR[31] = 1
115 *
116 * 0 4 8 12 16 20 24 28
117 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_BCSR_BASE 0xf8000000
Andy Fleming67431052007-04-23 02:54:25 -0500120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
Andy Fleming67431052007-04-23 02:54:25 -0500122
123/*Chip select 0 - Flash*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BR0_PRELIM 0xfe001001
125#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
Andy Fleming67431052007-04-23 02:54:25 -0500126
127/*Chip slelect 1 - BCSR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_BR1_PRELIM 0xf8000801
129#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
132#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
133#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
134#undef CONFIG_SYS_FLASH_CHECKSUM
135#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
136#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Andy Fleming67431052007-04-23 02:54:25 -0500137
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Andy Fleming67431052007-04-23 02:54:25 -0500139
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200140#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_FLASH_CFI
142#define CONFIG_SYS_FLASH_EMPTY_INFO
Andy Fleming67431052007-04-23 02:54:25 -0500143
Andy Fleming67431052007-04-23 02:54:25 -0500144/*
145 * SDRAM on the LocalBus
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
148#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Andy Fleming67431052007-04-23 02:54:25 -0500149
Andy Fleming67431052007-04-23 02:54:25 -0500150/*Chip select 2 - SDRAM*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_BR2_PRELIM 0xf0001861
152#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Andy Fleming67431052007-04-23 02:54:25 -0500153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
155#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
156#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
157#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Andy Fleming67431052007-04-23 02:54:25 -0500158
159/*
Andy Fleming67431052007-04-23 02:54:25 -0500160 * Common settings for all Local Bus SDRAM commands.
161 * At run time, either BSMA1516 (for CPU 1.1)
162 * or BSMA1617 (for CPU 1.0) (old)
163 * is OR'ed in too.
164 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500165#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
166 | LSDMR_PRETOACT7 \
167 | LSDMR_ACTTORW7 \
168 | LSDMR_BL8 \
169 | LSDMR_WRC4 \
170 | LSDMR_CL3 \
171 | LSDMR_RFEN \
Andy Fleming67431052007-04-23 02:54:25 -0500172 )
173
174/*
175 * The bcsr registers are connected to CS3 on MDS.
176 * The new memory map places bcsr at 0xf8000000.
177 *
178 * For BR3, need:
179 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
180 * port-size = 8-bits = BR[19:20] = 01
181 * no parity checking = BR[21:22] = 00
182 * GPMC for MSEL = BR[24:26] = 000
183 * Valid = BR[31] = 1
184 *
185 * 0 4 8 12 16 20 24 28
186 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
187 *
188 * For OR3, need:
189 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
190 * disable buffer ctrl OR[19] = 0
191 * CSNT OR[20] = 1
192 * ACS OR[21:22] = 11
193 * XACS OR[23] = 1
194 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
195 * SETA OR[28] = 0
196 * TRLX OR[29] = 1
197 * EHTR OR[30] = 1
198 * EAD extra time OR[31] = 1
199 *
200 * 0 4 8 12 16 20 24 28
201 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BCSR (0xf8000000)
Andy Fleming67431052007-04-23 02:54:25 -0500204
205/*Chip slelect 4 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_BR4_PRELIM 0xf8008801
207#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500208
209/*Chip select 5 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_BR5_PRELIM 0xf8010801
211#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
Andy Fleming67431052007-04-23 02:54:25 -0500212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_RAM_LOCK 1
214#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200215#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Andy Fleming67431052007-04-23 02:54:25 -0500216
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200217#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andy Fleming67431052007-04-23 02:54:25 -0500219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
221#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Andy Fleming67431052007-04-23 02:54:25 -0500222
223/* Serial Port */
224#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_NS16550_SERIAL
226#define CONFIG_SYS_NS16550_REG_SIZE 1
227#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andy Fleming67431052007-04-23 02:54:25 -0500228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_BAUDRATE_TABLE \
Andy Fleming67431052007-04-23 02:54:25 -0500230 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
233#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Andy Fleming67431052007-04-23 02:54:25 -0500234
Andy Fleming67431052007-04-23 02:54:25 -0500235/*
236 * I2C
237 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200238#define CONFIG_SYS_I2C
239#define CONFIG_SYS_I2C_FSL
240#define CONFIG_SYS_FSL_I2C_SPEED 400000
241#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
242#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
243#define CONFIG_SYS_FSL_I2C2_SPEED 400000
244#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
245#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
246#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
Andy Fleming67431052007-04-23 02:54:25 -0500248
249/*
250 * General PCI
251 * Memory Addresses are mapped 1-1. I/O is mapped from 0
252 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600253#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600254#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600255#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600257#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600258#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
260#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500261
Kumar Gala3f6f9d72010-12-17 10:13:19 -0600262#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600263#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600264#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600265#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600267#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600268#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
270#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500271
Kumar Gala5f7bbd12011-01-04 18:01:49 -0600272#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
273#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
274#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
275#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Andy Fleming67431052007-04-23 02:54:25 -0500276
Andy Flemingda9d4612007-08-14 00:14:25 -0500277#ifdef CONFIG_QE
278/*
279 * QE UEC ethernet configuration
280 */
281#define CONFIG_UEC_ETH
282#ifndef CONFIG_TSEC_ENET
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500283#define CONFIG_ETHPRIME "UEC0"
Andy Flemingda9d4612007-08-14 00:14:25 -0500284#endif
285#define CONFIG_PHY_MODE_NEED_CHANGE
286#define CONFIG_eTSEC_MDIO_BUS
287
288#ifdef CONFIG_eTSEC_MDIO_BUS
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200289#define CONFIG_MIIM_ADDRESS 0xE0024520
Andy Flemingda9d4612007-08-14 00:14:25 -0500290#endif
291
292#define CONFIG_UEC_ETH1 /* GETH1 */
293
294#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
296#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
297#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
298#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
299#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming865ff852011-04-13 00:37:12 -0500300#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100301#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500302#endif
303
304#define CONFIG_UEC_ETH2 /* GETH2 */
305
306#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
308#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
309#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
310#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
311#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming865ff852011-04-13 00:37:12 -0500312#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100313#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500314#endif
315#endif /* CONFIG_QE */
316
Haiying Wangf30ad492007-11-19 10:02:13 -0500317#if defined(CONFIG_PCI)
318
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200319#define CONFIG_PCI_PNP /* do pci plug-and-play */
Haiying Wangf30ad492007-11-19 10:02:13 -0500320
Andy Fleming67431052007-04-23 02:54:25 -0500321#undef CONFIG_EEPRO100
322#undef CONFIG_TULIP
323
324#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Andy Fleming67431052007-04-23 02:54:25 -0500326
327#endif /* CONFIG_PCI */
328
Andy Flemingda9d4612007-08-14 00:14:25 -0500329#if defined(CONFIG_TSEC_ENET)
330
Andy Fleming67431052007-04-23 02:54:25 -0500331#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500332#define CONFIG_TSEC1 1
333#define CONFIG_TSEC1_NAME "eTSEC0"
334#define CONFIG_TSEC2 1
335#define CONFIG_TSEC2_NAME "eTSEC1"
Andy Fleming67431052007-04-23 02:54:25 -0500336
337#define TSEC1_PHY_ADDR 2
338#define TSEC2_PHY_ADDR 3
339
340#define TSEC1_PHYIDX 0
341#define TSEC2_PHYIDX 0
342
Andy Fleming3a790132007-08-15 20:03:25 -0500343#define TSEC1_FLAGS TSEC_GIGABIT
344#define TSEC2_FLAGS TSEC_GIGABIT
345
Andy Flemingb96c83d2007-08-15 20:03:34 -0500346/* Options are: eTSEC[0-1] */
Andy Fleming67431052007-04-23 02:54:25 -0500347#define CONFIG_ETHPRIME "eTSEC0"
348
349#endif /* CONFIG_TSEC_ENET */
350
351/*
352 * Environment
353 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200354#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200356#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
357#define CONFIG_ENV_SIZE 0x2000
Andy Fleming67431052007-04-23 02:54:25 -0500358
359#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Andy Fleming67431052007-04-23 02:54:25 -0500361
Jon Loeliger2835e512007-06-13 13:22:08 -0500362/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500363 * BOOTP options
364 */
365#define CONFIG_BOOTP_BOOTFILESIZE
366#define CONFIG_BOOTP_BOOTPATH
367#define CONFIG_BOOTP_GATEWAY
368#define CONFIG_BOOTP_HOSTNAME
369
Jon Loeliger079a1362007-07-10 10:12:10 -0500370/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500371 * Command line configuration.
372 */
Kumar Gala1c9aa762008-09-22 23:40:42 -0500373#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500374#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500375
Andy Fleming67431052007-04-23 02:54:25 -0500376#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500377 #define CONFIG_CMD_PCI
Andy Fleming67431052007-04-23 02:54:25 -0500378#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500379
Andy Fleming67431052007-04-23 02:54:25 -0500380#undef CONFIG_WATCHDOG /* watchdog disabled */
381
382/*
383 * Miscellaneous configurable options
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500386#define CONFIG_CMDLINE_EDITING /* Command-line editing */
387#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500389#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500391#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500393#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
395#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
396#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500397
398/*
399 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500400 * have to be in the first 64 MB of memory, since this is
Andy Fleming67431052007-04-23 02:54:25 -0500401 * the maximum mapped by the Linux kernel during initialization.
402 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500403#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
404#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Andy Fleming67431052007-04-23 02:54:25 -0500405
Jon Loeliger2835e512007-06-13 13:22:08 -0500406#if defined(CONFIG_CMD_KGDB)
Andy Fleming67431052007-04-23 02:54:25 -0500407#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Andy Fleming67431052007-04-23 02:54:25 -0500408#endif
409
410/*
411 * Environment Configuration
412 */
413
414/* The mac addresses for all ethernet interface */
Andy Flemingda9d4612007-08-14 00:14:25 -0500415#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
416#define CONFIG_HAS_ETH0
Andy Fleming67431052007-04-23 02:54:25 -0500417#define CONFIG_HAS_ETH1
Andy Fleming67431052007-04-23 02:54:25 -0500418#define CONFIG_HAS_ETH2
Andy Flemingda9d4612007-08-14 00:14:25 -0500419#define CONFIG_HAS_ETH3
Andy Fleming67431052007-04-23 02:54:25 -0500420#endif
421
422#define CONFIG_IPADDR 192.168.1.253
423
424#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000425#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000426#define CONFIG_BOOTFILE "your.uImage"
Andy Fleming67431052007-04-23 02:54:25 -0500427
428#define CONFIG_SERVERIP 192.168.1.1
429#define CONFIG_GATEWAYIP 192.168.1.1
430#define CONFIG_NETMASK 255.255.255.0
431
432#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
433
Andy Fleming67431052007-04-23 02:54:25 -0500434#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
435
436#define CONFIG_BAUDRATE 115200
437
438#define CONFIG_EXTRA_ENV_SETTINGS \
439 "netdev=eth0\0" \
440 "consoledev=ttyS0\0" \
441 "ramdiskaddr=600000\0" \
442 "ramdiskfile=your.ramdisk.u-boot\0" \
443 "fdtaddr=400000\0" \
444 "fdtfile=your.fdt.dtb\0" \
445 "nfsargs=setenv bootargs root=/dev/nfs rw " \
446 "nfsroot=$serverip:$rootpath " \
447 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
448 "console=$consoledev,$baudrate $othbootargs\0" \
449 "ramargs=setenv bootargs root=/dev/ram rw " \
450 "console=$consoledev,$baudrate $othbootargs\0" \
451
Andy Fleming67431052007-04-23 02:54:25 -0500452#define CONFIG_NFSBOOTCOMMAND \
453 "run nfsargs;" \
454 "tftp $loadaddr $bootfile;" \
455 "tftp $fdtaddr $fdtfile;" \
456 "bootm $loadaddr - $fdtaddr"
457
Andy Fleming67431052007-04-23 02:54:25 -0500458#define CONFIG_RAMBOOTCOMMAND \
459 "run ramargs;" \
460 "tftp $ramdiskaddr $ramdiskfile;" \
461 "tftp $loadaddr $bootfile;" \
462 "bootm $loadaddr $ramdiskaddr"
463
464#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
465
466#endif /* __CONFIG_H */