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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc6097192002-11-03 00:24:07 +000021#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkc837dcb2004-01-20 23:12:12 +000022#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020023#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
wdenkc6097192002-11-03 00:24:07 +000024
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
wdenkc837dcb2004-01-20 23:12:12 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050028#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenkc6097192002-11-03 00:24:07 +000029
stroesea20b27a2004-12-16 18:05:42 +000030#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000031
32#define CONFIG_BAUDRATE 9600
wdenkc6097192002-11-03 00:24:07 +000033
wdenkc6097192002-11-03 00:24:07 +000034#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000035#undef CONFIG_BOOTCOMMAND
36
37#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000038
39#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000041
Ben Warren96e21f82008-10-27 23:50:15 -070042#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000043#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000045#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020046#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
47
Matthias Fuchs6f35c532007-06-24 17:41:21 +020048#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000049
50#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
51
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050052/*
53 * BOOTP options
54 */
55#define CONFIG_BOOTP_SUBNETMASK
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_DNS
60#define CONFIG_BOOTP_DNS2
61#define CONFIG_BOOTP_SEND_HOSTNAME
stroese9919f132003-05-23 11:38:22 +000062
Jon Loeliger49cf7e82007-07-05 19:52:35 -050063/*
64 * Command line configuration.
65 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050066#define CONFIG_CMD_PCI
67#define CONFIG_CMD_IRQ
68#define CONFIG_CMD_IDE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050069#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050070#define CONFIG_CMD_BSP
71#define CONFIG_CMD_EEPROM
72
wdenkc6097192002-11-03 00:24:07 +000073#define CONFIG_MAC_PARTITION
74#define CONFIG_DOS_PARTITION
75
stroesea20b27a2004-12-16 18:05:42 +000076#define CONFIG_SUPPORT_VFAT
77
wdenkc837dcb2004-01-20 23:12:12 +000078#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000079
wdenkc837dcb2004-01-20 23:12:12 +000080#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000081
82/*
83 * Miscellaneous configurable options
84 */
Tom Rinic6265f72015-06-02 11:12:20 -040085#undef CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkc6097192002-11-03 00:24:07 +000086
Jon Loeliger49cf7e82007-07-05 19:52:35 -050087#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000089#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000091#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
101#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000102
Stefan Roese550650d2010-09-20 16:05:31 +0200103#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese550650d2010-09-20 16:05:31 +0200104#define CONFIG_SYS_NS16550_SERIAL
105#define CONFIG_SYS_NS16550_REG_SIZE 1
106#define CONFIG_SYS_NS16550_CLK get_serial_clock()
107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
112#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000113
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200114#define CONFIG_CMDLINE_EDITING /* add command line history */
115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000117
wdenkc6097192002-11-03 00:24:07 +0000118/*-----------------------------------------------------------------------
119 * PCI stuff
120 *-----------------------------------------------------------------------
121 */
stroesea20b27a2004-12-16 18:05:42 +0000122#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
123#define PCI_HOST_FORCE 1 /* configure as pci host */
124#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000125
stroesea20b27a2004-12-16 18:05:42 +0000126#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000127#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea20b27a2004-12-16 18:05:42 +0000128#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
129#define CONFIG_PCI_PNP /* do pci plug-and-play */
130 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000131
stroesea20b27a2004-12-16 18:05:42 +0000132#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000133
stroesea20b27a2004-12-16 18:05:42 +0000134#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000135
stroesea20b27a2004-12-16 18:05:42 +0000136#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
139#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
140#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
141#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
142#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
143#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
144#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
145#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
146#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
Matthias Fuchs468ebf12012-11-02 14:30:34 +0100147#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000148
Matthias Fuchs82379b52009-09-07 17:00:41 +0200149#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
150
wdenkc6097192002-11-03 00:24:07 +0000151/*-----------------------------------------------------------------------
152 * IDE/ATA stuff
153 *-----------------------------------------------------------------------
154 */
wdenkc837dcb2004-01-20 23:12:12 +0000155#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
156#undef CONFIG_IDE_LED /* no led for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000157#define CONFIG_IDE_RESET 1 /* reset for ide supported */
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
160#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
163#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
166#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
167#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
wdenkc6097192002-11-03 00:24:07 +0000168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE 0x00000000
175#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
176#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
177#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
178#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000179
Matthias Fuchs3ba605d2009-01-02 12:18:49 +0100180#define CONFIG_PRAM 0 /* use pram variable to overwrite */
181
wdenkc6097192002-11-03 00:24:07 +0000182/*
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200188
wdenkc6097192002-11-03 00:24:07 +0000189/*-----------------------------------------------------------------------
190 * FLASH organization
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
193#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
196#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
199#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
200#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000201/*
202 * The following defines are added for buggy IOP480 byte interface.
203 * All other boards should use the standard values (CPCI405 etc.)
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
206#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
207#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000210
wdenkc6097192002-11-03 00:24:07 +0000211#if 0 /* Use NVRAM for environment variables */
212/*-----------------------------------------------------------------------
213 * NVRAM organization
214 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200215#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200216#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
217#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
wdenkc6097192002-11-03 00:24:07 +0000219
220#else /* Use EEPROM for environment variables */
221
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200222#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
224#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000225 /* total size of a CAT24WC16 is 2048 bytes */
wdenkc6097192002-11-03 00:24:07 +0000226#endif
227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
229#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
230#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
wdenkc6097192002-11-03 00:24:07 +0000231
232/*-----------------------------------------------------------------------
233 * I2C EEPROM (CAT24WC16) for environment
234 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000235#define CONFIG_SYS_I2C
236#define CONFIG_SYS_I2C_PPC4XX
237#define CONFIG_SYS_I2C_PPC4XX_CH0
238#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
239#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
242#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000243/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
245#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000246 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000247 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000249
wdenkc6097192002-11-03 00:24:07 +0000250/*
251 * Init Memory Controller:
252 *
253 * BR0/1 and OR0/1 (FLASH)
254 */
255
256#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
257#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
258
259/*-----------------------------------------------------------------------
260 * External Bus Controller (EBC) Setup
261 */
262
wdenkc837dcb2004-01-20 23:12:12 +0000263/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_EBC_PB0AP 0x92015480
265#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000266
wdenkc837dcb2004-01-20 23:12:12 +0000267/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_EBC_PB1AP 0x92015480
269#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000270
wdenkc837dcb2004-01-20 23:12:12 +0000271/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
273#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
274#define CONFIG_SYS_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000275
wdenkc837dcb2004-01-20 23:12:12 +0000276/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
278#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000279
wdenkc837dcb2004-01-20 23:12:12 +0000280/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
282#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
283#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000284
wdenkc837dcb2004-01-20 23:12:12 +0000285/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
287#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000288
wdenkc837dcb2004-01-20 23:12:12 +0000289/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
291#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
292#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000293
294/*-----------------------------------------------------------------------
295 * FPGA stuff
296 */
297/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_FPGA_MODE 0x00
299#define CONFIG_SYS_FPGA_STATUS 0x02
300#define CONFIG_SYS_FPGA_TS 0x04
301#define CONFIG_SYS_FPGA_TS_LOW 0x06
302#define CONFIG_SYS_FPGA_TS_CAP0 0x10
303#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
304#define CONFIG_SYS_FPGA_TS_CAP1 0x14
305#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
306#define CONFIG_SYS_FPGA_TS_CAP2 0x18
307#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
308#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
309#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000310
311/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
313#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
314#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
315#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
316#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
317#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000318
319/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
321#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
322#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
323#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
324#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
327#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000328
329/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
331#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
332#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
333#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
334#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000335
336/*-----------------------------------------------------------------------
337 * Definitions for initial stack pointer and data area (in data cache)
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200342#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200343#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000345
wdenkc6097192002-11-03 00:24:07 +0000346#endif /* __CONFIG_H */