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gerrit.cesnet.cz / github / trini / u-boot / 290e6e921f255fdee072d21539bbad16b9a3e714 / . / arch / m68k / include / asm / m520x.h
blob: e3d92c3fcc06bc4ee2c8ec294c2b647a089da211 [file] [log] [blame]
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]1/*
2 * m520x.h -- Definitions for Freescale Coldfire 520x
3 *
4 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]8 */
9
10#ifndef __M520X__
11#define __M520X__
12
13/* *** System Control Module (SCM) *** */
14#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
15#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
16#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
17#define MPROT_MTR 4
18#define MPROT_MTW 2
19#define MPROT_MPL 1
20
21#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
22#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
23#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
24
25#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
26
27#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
28#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
29#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
30#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
31#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
32#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
33
34#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
35#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
36#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
37#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
38#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
39#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
40#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
41
42#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
43#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
44#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
45#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
46#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
47
48#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
49#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
50#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
51
52#define PACR_SP 4
53#define PACR_WP 2
54#define PACR_TP 1
55
56#define SCM_BMT_BME (0x00000008)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]57#define SCM_BMT_BMT(x) ((x) & 0x07)
58#define SCM_BMT_BMT1024 (0x0000)
59#define SCM_BMT_BMT512 (0x0001)
60#define SCM_BMT_BMT256 (0x0002)
61#define SCM_BMT_BMT128 (0x0003)
62#define SCM_BMT_BMT64 (0x0004)
63#define SCM_BMT_BMT32 (0x0005)
64#define SCM_BMT_BMT16 (0x0006)
65#define SCM_BMT_BMT8 (0x0007)
66
67#define SCM_CWCR_RO (0x8000)
68#define SCM_CWCR_CWR_WH (0x0100)
69#define SCM_CWCR_CWE (0x0080)
70#define SCM_CWRI_WINDOW (0x0060)
71#define SCM_CWRI_RESET (0x0040)
72#define SCM_CWRI_INT_RESET (0x0020)
73#define SCM_CWRI_INT (0x0000)
74#define SCM_CWCR_CWT(x) (((x) & 0x001F))
75
76#define SCM_ISR_CFEI (0x02)
77#define SCM_ISR_CWIC (0x01)
78
79#define SCM_CFIER_ECFEI (0x01)
80
81#define SCM_CFLOC_LOC (0x80)
82
83#define SCM_CFATR_WRITE (0x80)
84#define SCM_CFATR_SZ32 (0x20)
85#define SCM_CFATR_SZ16 (0x10)
86#define SCM_CFATR_SZ08 (0x00)
87#define SCM_CFATR_CACHE (0x08)
88#define SCM_CFATR_MODE (0x02)
89#define SCM_CFATR_TYPE (0x01)
90
91/* *** Interrupt Controller (INTC) *** */
92#define INT0_LO_RSVD0 (0)
93#define INT0_LO_EPORT_F1 (1)
94#define INT0_LO_EPORT_F4 (2)
95#define INT0_LO_EPORT_F7 (3)
96#define INT1_LO_PIT0 (4)
97#define INT1_LO_PIT1 (5)
98/* 6 - 7 rsvd */
99#define INT0_LO_EDMA_00 (8)
100#define INT0_LO_EDMA_01 (9)
101#define INT0_LO_EDMA_02 (10)
102#define INT0_LO_EDMA_03 (11)
103#define INT0_LO_EDMA_04 (12)
104#define INT0_LO_EDMA_05 (13)
105#define INT0_LO_EDMA_06 (14)
106#define INT0_LO_EDMA_07 (15)
107#define INT0_LO_EDMA_08 (16)
108#define INT0_LO_EDMA_09 (17)
109#define INT0_LO_EDMA_10 (18)
110#define INT0_LO_EDMA_11 (19)
111#define INT0_LO_EDMA_12 (20)
112#define INT0_LO_EDMA_13 (21)
113#define INT0_LO_EDMA_14 (22)
114#define INT0_LO_EDMA_15 (23)
115#define INT0_LO_EDMA_ERR (24)
116#define INT0_LO_SCM_CWIC (25)
117#define INT0_LO_UART0 (26)
118#define INT0_LO_UART1 (27)
119#define INT0_LO_UART2 (28)
120/* 29 rsvd */
121#define INT0_LO_I2C (30)
122#define INT0_LO_QSPI (31)
123
124#define INT0_HI_DTMR0 (32)
125#define INT0_HI_DTMR1 (33)
126#define INT0_HI_DTMR2 (34)
127#define INT0_HI_DTMR3 (35)
128#define INT0_HI_FEC0_TXF (36)
129#define INT0_HI_FEC0_TXB (37)
130#define INT0_HI_FEC0_UN (38)
131#define INT0_HI_FEC0_RL (39)
132#define INT0_HI_FEC0_RXF (40)
133#define INT0_HI_FEC0_RXB (41)
134#define INT0_HI_FEC0_MII (42)
135#define INT0_HI_FEC0_LC (43)
136#define INT0_HI_FEC0_HBERR (44)
137#define INT0_HI_FEC0_GRA (45)
138#define INT0_HI_FEC0_EBERR (46)
139#define INT0_HI_FEC0_BABT (47)
140#define INT0_HI_FEC0_BABR (48)
141/* 49 - 61 rsvd */
142#define INT0_HI_SCMISR_CFEI (62)
143
144/* *** Reset Controller Module (RCM) *** */
145#define RCM_RCR_SOFTRST (0x80)
146#define RCM_RCR_FRCRSTOUT (0x40)
147
148#define RCM_RSR_SOFT (0x20)
149#define RCM_RSR_WDOG (0x10)
150#define RCM_RSR_POR (0x08)
151#define RCM_RSR_EXT (0x04)
152#define RCM_RSR_WDR_CORE (0x02)
153#define RCM_RSR_LOL (0x01)
154
155/* *** Chip Configuration Module (CCM) *** */
156#define CCM_CCR_CSC (0x0200)
157#define CCM_CCR_OSCFREQ (0x0080)
158#define CCM_CCR_LIMP (0x0040)
159#define CCM_CCR_LOAD (0x0020)
160#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3)
161#define CCM_CCR_OSC_MODE (0x0004)
162#define CCM_CCR_PLL_MODE (0x0002)
163#define CCM_CCR_RESERVED (0x0001)
164
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]165#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]166#define CCM_CIR_PRN(x) ((x) & 0x003F)
167
168/* *** General Purpose I/O (GPIO) *** */
169#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F)
170#define GPIO_PDR_BE(x) ((x) & 0x0F)
171#define GPIO_PDR_CS(x) (((x) & 0x07) << 1)
172#define GPIO_PDR_FECI2C(x) ((x) & 0x0F)
173#define GPIO_PDR_QSPI(x) ((x) & 0x0F)
174#define GPIO_PDR_TIMER(x) ((x) & 0x0F)
175#define GPIO_PDR_UART(x) ((x) & 0xFF)
176#define GPIO_PDR_FECH(x) ((x) & 0xFF)
177#define GPIO_PDR_FECL(x) ((x) & 0xFF)
178
179#define GPIO_PAR_FBCTL_OE (0x10)
180#define GPIO_PAR_FBCTL_TA (0x08)
181#define GPIO_PAR_FBCTL_RWB (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]182#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]183#define GPIO_PAR_FBCTL_TS_TS (0x03)
184#define GPIO_PAR_FBCTL_TS_DMA (0x02)
185
186#define GPIO_PAR_BE3 (0x08)
187#define GPIO_PAR_BE2 (0x04)
188#define GPIO_PAR_BE1 (0x02)
189#define GPIO_PAR_BE0 (0x01)
190
191#define GPIO_PAR_CS3 (0x08)
192#define GPIO_PAR_CS2 (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]193#define GPIO_PAR_CS1_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]194#define GPIO_PAR_CS1_CS1 (0x03)
195#define GPIO_PAR_CS1_SDCS1 (0x02)
196
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]197#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F)
198#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]199#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
200#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
201#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]202#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]203#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
204#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
205#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]206#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0)
207#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]208#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
209#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]210#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]211#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
212#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
213
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]214#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]215#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
216#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
217#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]218#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]219#define GPIO_PAR_QSPI_DIN_DIN (0x30)
220#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
221#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]222#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]223#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
224#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]225#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]226#define GPIO_PAR_QSPI_SCK_SCK (0x03)
227#define GPIO_PAR_QSPI_SCK_SCL (0x02)
228
229#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6)
230#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
231#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
232#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]233#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]234#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
235#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
236#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]237#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]238#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
239#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
240#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]241#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]242#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
243#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
244#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]245#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]246#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
247#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
248#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
249
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]250#define GPIO_PAR_UART1_UNMASK (0xF03F)
251#define GPIO_PAR_UART0_UNMASK (0xFFC0)
252#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]253#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
254#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
255#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]256#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]257#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
258#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
259#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
260#define GPIO_PAR_UART_U1TXD (0x0080)
261#define GPIO_PAR_UART_U1RXD (0x0040)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]262#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]263#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
264#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
265#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]266#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]267#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
268#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
269#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
270#define GPIO_PAR_UART_U0TXD (0x0002)
271#define GPIO_PAR_UART_U0RXD (0x0001)
272
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]273#define GPIO_PAR_FEC_7W_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]274#define GPIO_PAR_FEC_7W_FEC (0x0C)
275#define GPIO_PAR_FEC_7W_U1RTS (0x04)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]276#define GPIO_PAR_FEC_MII_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]277#define GPIO_PAR_FEC_MII_FEC (0x03)
278#define GPIO_PAR_FEC_MII_UnCTS (0x01)
279
280#define GPIO_PAR_IRQ_IRQ4 (0x01)
281
282#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6)
283#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
284#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
285#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]286#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F)
287#define GPIO_MSCR_FB_DUP_UNMASK (0xCF)
288#define GPIO_MSCR_FB_DLO_UNMASK (0xF3)
289#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]290
291#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
292#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
293#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]294#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF)
295#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3)
296#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]297
298#define MSCR_25VDDR (0x03)
299#define MSCR_18VDDR_FULL (0x02)
300#define MSCR_OPENDRAIN (0x01)
301#define MSCR_18VDDR_HALF (0x00)
302
303#define GPIO_DSCR_I2C(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]304#define GPIO_DSCR_I2C_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]305
306#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]307#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]308#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]309#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]310#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]311#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]312
313#define GPIO_DSCR_FEC(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]314#define GPIO_DSCR_FEC_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]315
316#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]317#define GPIO_DSCR_UART_UART1_UNMASK (0xCF)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]318#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]319#define GPIO_DSCR_UART_UART0_UNMASK (0xF3)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]320#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]321#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]322
323#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]324#define GPIO_DSCR_QSPI_UNMASK (0xFC)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]325
326#define DSCR_50PF (0x03)
327#define DSCR_30PF (0x02)
328#define DSCR_20PF (0x01)
329#define DSCR_10PF (0x00)
330
331/* *** Phase Locked Loop (PLL) *** */
332#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]333#define PLL_PODR_CPUDIV_UNMASK (0x0F)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]334#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]335#define PLL_PODR_BUSDIV_UNMASK (0xF0)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]336
337#define PLL_PCR_DITHEN (0x80)
338#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600[diff] [blame]339#define PLL_PCR_DITHDEV_UNMASK (0xF8)
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]340
341#endif /* __M520X__ */