arch/arm/dts/mt7622.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Sam Shih <sam.shih@mediatek.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/power/mt7629-power.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/ {
	compatible = "mediatek,mt7622";
	interrupt-parent = <&sysirq>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-frequency = <1300000000>;
		};
	};

	snfi: snfi@1100d000 {
		compatible = "mediatek,mtk-snfi-spi";
		reg = <0x1100d000 0x2000>;
		clocks = <&pericfg CLK_PERI_NFI_PD>,
			 <&pericfg CLK_PERI_SNFI_PD>;
		clock-names = "nfi_clk", "pad_clk";
		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
				  <&topckgen CLK_TOP_NFI_INFRA_SEL>;

		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
					 <&topckgen CLK_TOP_UNIVPLL2_D8>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>;
		arm,cpu-registers-not-fw-configured;
	};

	timer0: timer@10004000 {
		compatible = "mediatek,timer";
		reg = <0x10004000 0x80>;
		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>;
		clock-names = "system-clk";
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	infracfg: infracfg@10000000 {
		compatible = "mediatek,mt7622-infracfg",
			     "syscon";
		reg = <0x10000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: pericfg@10002000 {
		compatible = "mediatek,mt7622-pericfg", "syscon";
		reg = <0x10002000 0x1000>;
		#clock-cells = <1>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt7622-scpsys",
			     "syscon";
		#power-domain-cells = <1>;
		reg = <0x10006000 0x1000>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_HIF_SEL>;
		clock-names = "hif_sel";
	};

	sysirq: interrupt-controller@10200620 {
		compatible = "mediatek,sysirq";
		reg = <0x10200620 0x20>;
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	apmixedsys: apmixedsys@10209000 {
		compatible = "mediatek,mt7622-apmixedsys";
		reg = <0x10209000 0x1000>;
		#clock-cells = <1>;
	};

	topckgen: topckgen@10210000 {
		compatible = "mediatek,mt7622-topckgen";
		reg = <0x10210000 0x1000>;
		#clock-cells = <1>;
	};

	pinctrl: pinctrl@10211000 {
		compatible = "mediatek,mt7622-pinctrl";
		reg = <0x10211000 0x1000>;
		gpio: gpio-controller {
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	watchdog: watchdog@10212000 {
		compatible = "mediatek,wdt";
		reg = <0x10212000 0x800>;
	};

	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&watchdog>;
	};

	gic: interrupt-controller@10300000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10310000 0x1000>,
		      <0x10320000 0x1000>,
		      <0x10340000 0x2000>,
		      <0x10360000 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,hsuart";
		reg = <0x11002000 0x400>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART0_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7622-mmc";
		reg = <0x11230000 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
			 <&topckgen CLK_TOP_MSDC50_0_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	mmc1: mmc@11240000 {
		compatible = "mediatek,mt7622-mmc";
		reg = <0x11240000 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
			 <&topckgen CLK_TOP_AXI_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	pciesys: pciesys@1a100800 {
		compatible = "mediatek,mt7622-pciesys", "syscon";
		reg = <0x1a100800 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
		compatible = "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0x1a140000 0x1000>,
		      <0x1a143000 0x1000>,
		      <0x1a145000 0x1000>;
		reg-names = "subsys", "port0", "port1";
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
			 <&pciesys CLK_PCIE_P1_MAC_EN>,
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P0_AUX_EN>,
			 <&pciesys CLK_PCIE_P1_AUX_EN>,
			 <&pciesys CLK_PCIE_P0_AXI_EN>,
			 <&pciesys CLK_PCIE_P1_AXI_EN>,
			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
		power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
		status = "disabled";

		pcie0: pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges;
			status = "disabled";

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
					<0 0 0 2 &pcie_intc0 1>,
					<0 0 0 3 &pcie_intc0 2>,
					<0 0 0 4 &pcie_intc0 3>;
			pcie_intc0: interrupt-controller {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <1>;
			};
		};

		pcie1: pcie@1,0 {
			reg = <0x0800 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges;
			status = "disabled";

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
					<0 0 0 2 &pcie_intc1 1>,
					<0 0 0 3 &pcie_intc1 2>,
					<0 0 0 4 &pcie_intc1 3>;
			pcie_intc1: interrupt-controller {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <1>;
			};
		};
	};

	sata: sata@1a200000 {
		compatible = "mediatek,mtk-ahci";
		reg = <0x1a200000 0x1100>;
		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
			<&pciesys MT7622_SATA_PHY_SW_RST>,
			<&pciesys MT7622_SATA_PHY_REG_RST>;
		reset-names = "axi", "sw", "reg";
		mediatek,phy-mode = <&pciesys>;
		ports-implemented = <0x1>;
		phys = <&sata_port PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		status = "okay";
	};

	sata_phy: sata-phy@1a243000 {
		compatible = "mediatek,generic-tphy-v1";
		reg = <0x1a243000 0x0100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		status = "okay";

		sata_port: sata-phy@1a243000 {
			reg = <0x1a243000 0x0100>;
			clocks = <&topckgen CLK_TOP_ETH_500M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt7622-ethsys", "syscon";
		reg = <0x1b000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt7622-eth", "syscon";
		reg = <0x1b100000 0x20000>;
		clocks = <&topckgen CLK_TOP_ETH_SEL>,
			 <&ethsys CLK_ETH_ESW_EN>,
			 <&ethsys CLK_ETH_GP0_EN>,
			 <&ethsys CLK_ETH_GP1_EN>,
			 <&ethsys CLK_ETH_GP2_EN>,
			 <&sgmiisys CLK_SGMII_TX250M_EN>,
			 <&sgmiisys CLK_SGMII_RX250M_EN>,
			 <&sgmiisys CLK_SGMII_CDR_REF>,
			 <&sgmiisys CLK_SGMII_CDR_FB>,
			 <&topckgen CLK_TOP_SGMIIPLL>,
			 <&apmixedsys CLK_APMIXED_ETH2PLL>;
		clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
			      "sgmii_tx250m", "sgmii_rx250m",
			      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
			      "eth2pll";
		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
		resets = <&ethsys ETHSYS_FE_RST>;
		reset-names = "fe";
		mediatek,ethsys = <&ethsys>;
		mediatek,sgmiisys = <&sgmiisys>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sgmiisys: sgmiisys@1b128000 {
		compatible = "mediatek,mt7622-sgmiisys", "syscon";
		reg = <0x1b128000 0x3000>;
		#clock-cells = <1>;
	};

	pwm: pwm@11006000 {
		compatible = "mediatek,mt7622-pwm";
		reg = <0x11006000 0x1000>;
		#clock-cells = <1>;
		#pwm-cells = <2>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_PWM_SEL>,
			 <&pericfg CLK_PERI_PWM_PD>,
			 <&pericfg CLK_PERI_PWM1_PD>,
			 <&pericfg CLK_PERI_PWM2_PD>,
			 <&pericfg CLK_PERI_PWM3_PD>,
			 <&pericfg CLK_PERI_PWM4_PD>,
			 <&pericfg CLK_PERI_PWM5_PD>,
			 <&pericfg CLK_PERI_PWM6_PD>;
		clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
			      "pwm5", "pwm6";
		status = "disabled";
	};

};