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Allen Martin77c42e82013-03-16 18:58:13 +00001/*
2 * NVIDIA Tegra SPI controller (T114 and later)
3 *
4 * Copyright (c) 2010-2013 NVIDIA Corporation
5 *
Tom Rini5b8031c2016-01-14 22:05:13 -05006 * SPDX-License-Identifier: GPL-2.0
Allen Martin77c42e82013-03-16 18:58:13 +00007 */
8
9#include <common.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060010#include <dm.h>
Allen Martin77c42e82013-03-16 18:58:13 +000011#include <asm/io.h>
Allen Martin77c42e82013-03-16 18:58:13 +000012#include <asm/arch/clock.h>
13#include <asm/arch-tegra/clk_rst.h>
Allen Martin77c42e82013-03-16 18:58:13 +000014#include <spi.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060015#include "tegra_spi.h"
Allen Martin77c42e82013-03-16 18:58:13 +000016
17DECLARE_GLOBAL_DATA_PTR;
18
19/* COMMAND1 */
Jagan Tekif6922482015-10-23 01:39:06 +053020#define SPI_CMD1_GO BIT(31)
21#define SPI_CMD1_M_S BIT(30)
Jagan Teki76538ec2015-10-23 01:03:10 +053022#define SPI_CMD1_MODE_MASK GENMASK(1, 0)
Allen Martin77c42e82013-03-16 18:58:13 +000023#define SPI_CMD1_MODE_SHIFT 28
Jagan Teki76538ec2015-10-23 01:03:10 +053024#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
Allen Martin77c42e82013-03-16 18:58:13 +000025#define SPI_CMD1_CS_SEL_SHIFT 26
Jagan Tekif6922482015-10-23 01:39:06 +053026#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
27#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
28#define SPI_CMD1_CS_POL_INACTIVE1 BIT(23)
29#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
30#define SPI_CMD1_CS_SW_HW BIT(21)
31#define SPI_CMD1_CS_SW_VAL BIT(20)
Jagan Teki76538ec2015-10-23 01:03:10 +053032#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
Allen Martin77c42e82013-03-16 18:58:13 +000033#define SPI_CMD1_IDLE_SDA_SHIFT 18
Jagan Tekif6922482015-10-23 01:39:06 +053034#define SPI_CMD1_BIDIR BIT(17)
35#define SPI_CMD1_LSBI_FE BIT(16)
36#define SPI_CMD1_LSBY_FE BIT(15)
37#define SPI_CMD1_BOTH_EN_BIT BIT(14)
38#define SPI_CMD1_BOTH_EN_BYTE BIT(13)
39#define SPI_CMD1_RX_EN BIT(12)
40#define SPI_CMD1_TX_EN BIT(11)
41#define SPI_CMD1_PACKED BIT(5)
Jagan Teki76538ec2015-10-23 01:03:10 +053042#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
Allen Martin77c42e82013-03-16 18:58:13 +000043#define SPI_CMD1_BIT_LEN_SHIFT 0
44
45/* COMMAND2 */
Jagan Tekif6922482015-10-23 01:39:06 +053046#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
Jagan Teki76538ec2015-10-23 01:03:10 +053047#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
Jagan Tekif6922482015-10-23 01:39:06 +053048#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
Jagan Teki76538ec2015-10-23 01:03:10 +053049#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
Allen Martin77c42e82013-03-16 18:58:13 +000050
51/* TRANSFER STATUS */
Jagan Tekif6922482015-10-23 01:39:06 +053052#define SPI_XFER_STS_RDY BIT(30)
Allen Martin77c42e82013-03-16 18:58:13 +000053
54/* FIFO STATUS */
Jagan Tekif6922482015-10-23 01:39:06 +053055#define SPI_FIFO_STS_CS_INACTIVE BIT(31)
56#define SPI_FIFO_STS_FRAME_END BIT(30)
57#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
58#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
59#define SPI_FIFO_STS_ERR BIT(8)
60#define SPI_FIFO_STS_TX_FIFO_OVF BIT(7)
61#define SPI_FIFO_STS_TX_FIFO_UNR BIT(6)
62#define SPI_FIFO_STS_RX_FIFO_OVF BIT(5)
63#define SPI_FIFO_STS_RX_FIFO_UNR BIT(4)
64#define SPI_FIFO_STS_TX_FIFO_FULL BIT(3)
65#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
66#define SPI_FIFO_STS_RX_FIFO_FULL BIT(1)
67#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
Allen Martin77c42e82013-03-16 18:58:13 +000068
69#define SPI_TIMEOUT 1000
70#define TEGRA_SPI_MAX_FREQ 52000000
71
72struct spi_regs {
73 u32 command1; /* 000:SPI_COMMAND1 register */
74 u32 command2; /* 004:SPI_COMMAND2 register */
75 u32 timing1; /* 008:SPI_CS_TIM1 register */
76 u32 timing2; /* 00c:SPI_CS_TIM2 register */
77 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
78 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
79 u32 tx_data; /* 018:SPI_TX_DATA register */
80 u32 rx_data; /* 01c:SPI_RX_DATA register */
81 u32 dma_ctl; /* 020:SPI_DMA_CTL register */
82 u32 dma_blk; /* 024:SPI_DMA_BLK register */
83 u32 rsvd[56]; /* 028-107 reserved */
84 u32 tx_fifo; /* 108:SPI_FIFO1 register */
85 u32 rsvd2[31]; /* 10c-187 reserved */
86 u32 rx_fifo; /* 188:SPI_FIFO2 register */
87 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
88};
89
Simon Glassfda6fac2014-10-13 23:42:13 -060090struct tegra114_spi_priv {
Allen Martin77c42e82013-03-16 18:58:13 +000091 struct spi_regs *regs;
92 unsigned int freq;
93 unsigned int mode;
94 int periph_id;
95 int valid;
Simon Glassfda6fac2014-10-13 23:42:13 -060096 int last_transaction_us;
Allen Martin77c42e82013-03-16 18:58:13 +000097};
98
Simon Glassfda6fac2014-10-13 23:42:13 -060099static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000100{
Simon Glassfda6fac2014-10-13 23:42:13 -0600101 struct tegra_spi_platdata *plat = bus->platdata;
Simon Glassfda6fac2014-10-13 23:42:13 -0600102
Simon Glass28a3e5a2017-07-25 08:30:05 -0600103 plat->base = dev_read_addr(bus);
Simon Glass000f15f2017-07-25 08:30:00 -0600104 plat->periph_id = clock_decode_periph_id(bus);
Simon Glassfda6fac2014-10-13 23:42:13 -0600105
106 if (plat->periph_id == PERIPH_ID_NONE) {
107 debug("%s: could not decode periph id %d\n", __func__,
108 plat->periph_id);
109 return -FDT_ERR_NOTFOUND;
110 }
111
112 /* Use 500KHz as a suitable default */
Simon Glass28a3e5a2017-07-25 08:30:05 -0600113 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
114 500000);
115 plat->deactivate_delay_us = dev_read_u32_default(bus,
116 "spi-deactivate-delay", 0);
Simon Glassfda6fac2014-10-13 23:42:13 -0600117 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
118 __func__, plat->base, plat->periph_id, plat->frequency,
119 plat->deactivate_delay_us);
120
121 return 0;
Allen Martin77c42e82013-03-16 18:58:13 +0000122}
123
Simon Glassfda6fac2014-10-13 23:42:13 -0600124static int tegra114_spi_probe(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000125{
Simon Glassfda6fac2014-10-13 23:42:13 -0600126 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
127 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Simon Glass635c2512015-06-05 14:39:33 -0600128 struct spi_regs *regs;
Simon Glass20edd1a2015-06-05 14:39:35 -0600129 ulong rate;
Simon Glassfda6fac2014-10-13 23:42:13 -0600130
131 priv->regs = (struct spi_regs *)plat->base;
Simon Glass635c2512015-06-05 14:39:33 -0600132 regs = priv->regs;
Simon Glassfda6fac2014-10-13 23:42:13 -0600133
134 priv->last_transaction_us = timer_get_us();
135 priv->freq = plat->frequency;
136 priv->periph_id = plat->periph_id;
137
Simon Glass20edd1a2015-06-05 14:39:35 -0600138 /*
139 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
140 * back to the oscillator if that is too fast.
141 */
142 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
143 priv->freq);
144 if (rate > priv->freq + 100000) {
145 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
146 priv->freq);
147 if (rate != priv->freq) {
148 printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
149 bus->name, priv->freq, rate);
150 }
151 }
Simon Glass4a7b9ee2017-05-31 17:57:18 -0600152 udelay(plat->deactivate_delay_us);
Allen Martin77c42e82013-03-16 18:58:13 +0000153
154 /* Clear stale status here */
155 setbits_le32(&regs->fifo_status,
156 SPI_FIFO_STS_ERR |
157 SPI_FIFO_STS_TX_FIFO_OVF |
158 SPI_FIFO_STS_TX_FIFO_UNR |
159 SPI_FIFO_STS_RX_FIFO_OVF |
160 SPI_FIFO_STS_RX_FIFO_UNR |
161 SPI_FIFO_STS_TX_FIFO_FULL |
162 SPI_FIFO_STS_TX_FIFO_EMPTY |
163 SPI_FIFO_STS_RX_FIFO_FULL |
164 SPI_FIFO_STS_RX_FIFO_EMPTY);
165 debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
166
Simon Glass635c2512015-06-05 14:39:33 -0600167 setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
168 (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
Allen Martin77c42e82013-03-16 18:58:13 +0000169 debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
170
171 return 0;
172}
173
Simon Glassfda6fac2014-10-13 23:42:13 -0600174/**
175 * Activate the CS by driving it LOW
176 *
177 * @param slave Pointer to spi_slave to which controller has to
178 * communicate with
179 */
180static void spi_cs_activate(struct udevice *dev)
Allen Martin77c42e82013-03-16 18:58:13 +0000181{
Simon Glassfda6fac2014-10-13 23:42:13 -0600182 struct udevice *bus = dev->parent;
183 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
184 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Allen Martin77c42e82013-03-16 18:58:13 +0000185
Simon Glassfda6fac2014-10-13 23:42:13 -0600186 /* If it's too soon to do another transaction, wait */
187 if (pdata->deactivate_delay_us &&
188 priv->last_transaction_us) {
189 ulong delay_us; /* The delay completed so far */
190 delay_us = timer_get_us() - priv->last_transaction_us;
191 if (delay_us < pdata->deactivate_delay_us)
192 udelay(pdata->deactivate_delay_us - delay_us);
193 }
194
195 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
Allen Martin77c42e82013-03-16 18:58:13 +0000196}
197
Simon Glassfda6fac2014-10-13 23:42:13 -0600198/**
199 * Deactivate the CS by driving it HIGH
200 *
201 * @param slave Pointer to spi_slave to which controller has to
202 * communicate with
203 */
204static void spi_cs_deactivate(struct udevice *dev)
Allen Martin77c42e82013-03-16 18:58:13 +0000205{
Simon Glassfda6fac2014-10-13 23:42:13 -0600206 struct udevice *bus = dev->parent;
207 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
208 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Allen Martin77c42e82013-03-16 18:58:13 +0000209
Simon Glassfda6fac2014-10-13 23:42:13 -0600210 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
211
212 /* Remember time of this transaction so we can honour the bus delay */
213 if (pdata->deactivate_delay_us)
214 priv->last_transaction_us = timer_get_us();
215
216 debug("Deactivate CS, bus '%s'\n", bus->name);
Allen Martin77c42e82013-03-16 18:58:13 +0000217}
218
Simon Glassfda6fac2014-10-13 23:42:13 -0600219static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
220 const void *data_out, void *data_in,
221 unsigned long flags)
Allen Martin77c42e82013-03-16 18:58:13 +0000222{
Simon Glassfda6fac2014-10-13 23:42:13 -0600223 struct udevice *bus = dev->parent;
224 struct tegra114_spi_priv *priv = dev_get_priv(bus);
225 struct spi_regs *regs = priv->regs;
Allen Martin77c42e82013-03-16 18:58:13 +0000226 u32 reg, tmpdout, tmpdin = 0;
227 const u8 *dout = data_out;
228 u8 *din = data_in;
229 int num_bytes;
230 int ret;
231
232 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
Simon Glassfda6fac2014-10-13 23:42:13 -0600233 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
Allen Martin77c42e82013-03-16 18:58:13 +0000234 if (bitlen % 8)
235 return -1;
236 num_bytes = bitlen / 8;
237
238 ret = 0;
239
Simon Glass635c2512015-06-05 14:39:33 -0600240 if (flags & SPI_XFER_BEGIN)
241 spi_cs_activate(dev);
242
Allen Martin77c42e82013-03-16 18:58:13 +0000243 /* clear all error status bits */
244 reg = readl(&regs->fifo_status);
245 writel(reg, &regs->fifo_status);
246
Allen Martin77c42e82013-03-16 18:58:13 +0000247 clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
248 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
Simon Glassfda6fac2014-10-13 23:42:13 -0600249 (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
Allen Martin77c42e82013-03-16 18:58:13 +0000250
251 /* set xfer size to 1 block (32 bits) */
252 writel(0, &regs->dma_blk);
253
Allen Martin77c42e82013-03-16 18:58:13 +0000254 /* handle data in 32-bit chunks */
255 while (num_bytes > 0) {
256 int bytes;
Allen Martin77c42e82013-03-16 18:58:13 +0000257 int tm, i;
258
259 tmpdout = 0;
260 bytes = (num_bytes > 4) ? 4 : num_bytes;
261
262 if (dout != NULL) {
263 for (i = 0; i < bytes; ++i)
264 tmpdout = (tmpdout << 8) | dout[i];
265 dout += bytes;
266 }
267
268 num_bytes -= bytes;
269
Yen Lin60acde42013-12-18 11:18:46 -0700270 /* clear ready bit */
271 setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
272
Allen Martin77c42e82013-03-16 18:58:13 +0000273 clrsetbits_le32(&regs->command1,
274 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
275 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
276 writel(tmpdout, &regs->tx_fifo);
277 setbits_le32(&regs->command1, SPI_CMD1_GO);
278
279 /*
280 * Wait for SPI transmit FIFO to empty, or to time out.
281 * The RX FIFO status will be read and cleared last
282 */
Yen Lin60acde42013-12-18 11:18:46 -0700283 for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
Allen Martin77c42e82013-03-16 18:58:13 +0000284 u32 fifo_status, xfer_status;
285
Allen Martin77c42e82013-03-16 18:58:13 +0000286 xfer_status = readl(&regs->xfer_status);
287 if (!(xfer_status & SPI_XFER_STS_RDY))
288 continue;
289
Yen Lin60acde42013-12-18 11:18:46 -0700290 fifo_status = readl(&regs->fifo_status);
Allen Martin77c42e82013-03-16 18:58:13 +0000291 if (fifo_status & SPI_FIFO_STS_ERR) {
292 debug("%s: got a fifo error: ", __func__);
293 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
294 debug("tx FIFO overflow ");
295 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
296 debug("tx FIFO underrun ");
297 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
298 debug("rx FIFO overflow ");
299 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
300 debug("rx FIFO underrun ");
301 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
302 debug("tx FIFO full ");
303 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
304 debug("tx FIFO empty ");
305 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
306 debug("rx FIFO full ");
307 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
308 debug("rx FIFO empty ");
309 debug("\n");
310 break;
311 }
312
313 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
314 tmpdin = readl(&regs->rx_fifo);
Allen Martin77c42e82013-03-16 18:58:13 +0000315
316 /* swap bytes read in */
317 if (din != NULL) {
318 for (i = bytes - 1; i >= 0; --i) {
319 din[i] = tmpdin & 0xff;
320 tmpdin >>= 8;
321 }
322 din += bytes;
323 }
Yen Lin60acde42013-12-18 11:18:46 -0700324
325 /* We can exit when we've had both RX and TX */
326 break;
Allen Martin77c42e82013-03-16 18:58:13 +0000327 }
328 }
329
330 if (tm >= SPI_TIMEOUT)
331 ret = tm;
332
333 /* clear ACK RDY, etc. bits */
334 writel(readl(&regs->fifo_status), &regs->fifo_status);
335 }
336
337 if (flags & SPI_XFER_END)
Simon Glassfda6fac2014-10-13 23:42:13 -0600338 spi_cs_deactivate(dev);
Allen Martin77c42e82013-03-16 18:58:13 +0000339
340 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
341 __func__, tmpdin, readl(&regs->fifo_status));
342
343 if (ret) {
344 printf("%s: timeout during SPI transfer, tm %d\n",
345 __func__, ret);
346 return -1;
347 }
348
Simon Glassfda6fac2014-10-13 23:42:13 -0600349 return ret;
350}
351
352static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
353{
354 struct tegra_spi_platdata *plat = bus->platdata;
355 struct tegra114_spi_priv *priv = dev_get_priv(bus);
356
357 if (speed > plat->frequency)
358 speed = plat->frequency;
359 priv->freq = speed;
360 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
361
Allen Martin77c42e82013-03-16 18:58:13 +0000362 return 0;
363}
Simon Glassfda6fac2014-10-13 23:42:13 -0600364
365static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
366{
367 struct tegra114_spi_priv *priv = dev_get_priv(bus);
368
369 priv->mode = mode;
370 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
371
372 return 0;
373}
374
375static const struct dm_spi_ops tegra114_spi_ops = {
Simon Glassfda6fac2014-10-13 23:42:13 -0600376 .xfer = tegra114_spi_xfer,
377 .set_speed = tegra114_spi_set_speed,
378 .set_mode = tegra114_spi_set_mode,
379 /*
380 * cs_info is not needed, since we require all chip selects to be
381 * in the device tree explicitly
382 */
383};
384
385static const struct udevice_id tegra114_spi_ids[] = {
386 { .compatible = "nvidia,tegra114-spi" },
387 { }
388};
389
390U_BOOT_DRIVER(tegra114_spi) = {
391 .name = "tegra114_spi",
392 .id = UCLASS_SPI,
393 .of_match = tegra114_spi_ids,
394 .ops = &tegra114_spi_ops,
395 .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
396 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
397 .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
Simon Glassfda6fac2014-10-13 23:42:13 -0600398 .probe = tegra114_spi_probe,
399};